Recruitment
SemiTO-V, RISC-V Student Team - Recruitment
SemiTO-V is a RISC-V-oriented student Team that uses the open standard RISC-V ISA to create custom processors, firmware, and software, as well as its own PCB designs, sharing them fully open source
By joining the Team, students will have the opportunity to work in a broad-spectrum of RISC-V related projects that include development of cores and processors from scratch, circuits around processors and better software compatibility for RISC-V ecosystem.
What exactly is RISC-V?
RISC-V is an open standard ISA (Instruction Set Architecture). An ISA is essentially a blueprint or vocabulary that dictates how software communicates with the processor and hardware around. It defines the set of instructions a processor can understand and execute.
The "RISC" part stands for Reduced Instruction Set Computer, which means its design uses a smaller, more efficient set of instructions compared to older architecture. This simplicity makes the processors faster, smaller, and more power-efficient.
RISC-V is completely open, allowing anyone to contribute and use it in their designs. This democratizes the processor industry and enables the creation of fully open-source computing.
What does the Team do?
SemiTO-V Team is currently working on making its own 32 bit RISC-V based core. So far, the team has designed an expansion card circuit for Framework laptops based on RP2350 and developed a software library to support it.
Task forces:
- CPU Task Force:
- Design and use cores based on RISC-V ISA (RV32/RV64), add custom instructions and modules
- Implement MCUs/SoCs targeting FPGAs
- Explore advanced features such as pipelining and parallel processing (potentially for HPC)
- Design ASIC for tapeout (in the future)
- Circuit Task Force:
- Design open source PCBs based on either FPGAs running the team’s RISC-V based processors or RISC-V based CPU chips already available on the market
- Test RISC-V based hardware on the market and embed them in various practical/demo applications
- Interface with peripherals
- Make the team’s own processors wireless-enabled by embedding RF circuits for different protocols (WiFi, Bluetooth, Zigbee).
- Software Task Force:
- Develop/improve bare-metal firmware, RTOS (FreeRTOS, Zephyr OS, RT-Thread) and GPOS (Linux for RV64) implementations
- Port and optimize compilers for the Team’s processors
- Contribute to the software that are important for RISC-V ecosystem (Linux kernel, LLVM, vector libraries)
- Create SDKs, toolchains and simulators for the Team’s designs
- Develop benchmarks/configure existing ones to run tests on the Team’s designs and existing ones, comparing performance of RISC-V technologies
- Public Relations:
- Inform the public about the team and RISC-V ecosystem in general
- Make vector and raster visual designs (without AI)
SemiTO-V works on diverse RISC-V projects in addition to core design.
Students with expertise relevant to the Team's task forces or those interested in proposing new RISC-V-related initiatives are welcome to join the Team through this form.
Applications accepted year-round.
Students new to RISC-V but interested in learning within a community are welcome to join the Telegram chat, where RISC-V topics are discussed and public events are announced.
FOR MORE INFORMATION AND UPDATES:
Website
By joining the Team, students will have the opportunity to work in a broad-spectrum of RISC-V related projects that include development of cores and processors from scratch, circuits around processors and better software compatibility for RISC-V ecosystem.
What exactly is RISC-V?
RISC-V is an open standard ISA (Instruction Set Architecture). An ISA is essentially a blueprint or vocabulary that dictates how software communicates with the processor and hardware around. It defines the set of instructions a processor can understand and execute.
The "RISC" part stands for Reduced Instruction Set Computer, which means its design uses a smaller, more efficient set of instructions compared to older architecture. This simplicity makes the processors faster, smaller, and more power-efficient.
RISC-V is completely open, allowing anyone to contribute and use it in their designs. This democratizes the processor industry and enables the creation of fully open-source computing.
What does the Team do?
SemiTO-V Team is currently working on making its own 32 bit RISC-V based core. So far, the team has designed an expansion card circuit for Framework laptops based on RP2350 and developed a software library to support it.
Task forces:
- CPU Task Force:
- Design and use cores based on RISC-V ISA (RV32/RV64), add custom instructions and modules
- Implement MCUs/SoCs targeting FPGAs
- Explore advanced features such as pipelining and parallel processing (potentially for HPC)
- Design ASIC for tapeout (in the future)
- Circuit Task Force:
- Design open source PCBs based on either FPGAs running the team’s RISC-V based processors or RISC-V based CPU chips already available on the market
- Test RISC-V based hardware on the market and embed them in various practical/demo applications
- Interface with peripherals
- Make the team’s own processors wireless-enabled by embedding RF circuits for different protocols (WiFi, Bluetooth, Zigbee).
- Software Task Force:
- Develop/improve bare-metal firmware, RTOS (FreeRTOS, Zephyr OS, RT-Thread) and GPOS (Linux for RV64) implementations
- Port and optimize compilers for the Team’s processors
- Contribute to the software that are important for RISC-V ecosystem (Linux kernel, LLVM, vector libraries)
- Create SDKs, toolchains and simulators for the Team’s designs
- Develop benchmarks/configure existing ones to run tests on the Team’s designs and existing ones, comparing performance of RISC-V technologies
- Public Relations:
- Inform the public about the team and RISC-V ecosystem in general
- Make vector and raster visual designs (without AI)
SemiTO-V works on diverse RISC-V projects in addition to core design.
Students with expertise relevant to the Team's task forces or those interested in proposing new RISC-V-related initiatives are welcome to join the Team through this form.
Applications accepted year-round.
Students new to RISC-V but interested in learning within a community are welcome to join the Telegram chat, where RISC-V topics are discussed and public events are announced.
FOR MORE INFORMATION AND UPDATES:
Website