Ph.D. in Ingegneria Informatica E Dei Sistemi , 18th cycle (2003-2005)
Ph.D. obtained in 2006
Dissertation:
Test Techniques for Systems-on-a-Chip.
Tutors:
Matteo Sonza ReordaProfile
Research interests
Scientific branch
(Area 0009 - Industrial and information engineering)
Awards and Honors
Teaching
Collegi of the degree programmes
Other activities and projects related to teaching
Lecturer of the following courses:
- Architetture dei Sistemi di Elaborazione (1st year Master)
- Computer Science (1st year Bachelor)
Research
Research groups
Research projects
Projects funded by competitive calls
- ARBoard - Test di complessi circuiti stampati tramite Realtà Aumentata con estrazione automatica delle caratteristiche topologiche , (2025-2026) - Responsabile Scientifico
Corporate-funded and donor-funded research
Projects funded by commercial contracts
- AURIXTM NVM Test Strategies enabling Minimal Pincount Concurrent FE Insertion for eNVM Reduced test costs and Diagnosis , (2026-2026) - Componente gruppo di Ricerca
Commercial Research - Implementation and Evaluation of a Stress Test Flow based on the execution of structural and/or functional patterns in a System Level and BurnIn/WLBI context on microcontrollers of the Stellar family in P28 FD-SOI technology at 28nm , (periodo sconosciuto) - Responsabile Scientifico
Commercial Research - TC4xx NVM Test Strategies enabling Minimal Pincount FE Insertion for reduced test costs , (2025-2025) - Componente gruppo di Ricerca
Commercial Research - Metodologie per la massimizzazione della stress-coverage mediante applicazione di test strutturali e funzionali in ambiente System Level Test/Burn-In , (2024-2025) - Responsabile Scientifico
Commercial Research - Misurazione micrometrica di distanze assolute con metodi basati su triangolazione ottica , (2024-2025) - Responsabile Scientifico
Commercial Research - Contratto di ricerca tra il Politecnico di Torino (DISAT) e la Società Dana-TM4 Italia S.r.l. per la realizzazione del Progetto di Ricerca “Analisi dello stato dell’arte di power modules, Studio e Sviluppo di una nuova generazione di power module LV, analisi di affidabilità e test di qualifica” , (2023-2025) - Responsabile Scientifico
Commercial Research - Colored NVM bitmap and repair integration with statistical evaluation in production for Aurix3G product family , (2023-2024) - Responsabile Scientifico
Commercial Research - Metodologie per la massimizzazione della stress-coverage mediante applicazione di test strutturali e funzionali in ambiente System Level Test/Burn-In e Utilizzo di test funzionali per ridurre l’over-killing dovuto alle condizioni di , (2023-2024) - Responsabile Scientifico
Commercial Research - Study of solutions for internal analog signals measurement and delivery of information across the chip in digital form , (2023-2024) - Responsabile Scientifico
Commercial Research - Colored NVM bitmap integration and validation in Aurix3G product family and A3G NVM Read Redundancy Analysis PBIST Concurrent Power Aware BIST Test Strategies enabling Minimal Pincount FE Insertion , (2023-2023) - Responsabile Scientifico
Commercial Research - Generazione automatica e algoritmica di stimoli per lo stress (burn-in) di dispositivi SoC , (2022-2023) - Responsabile Scientifico
Commercial Research - Colored bitmap integration in Aurix2G including demonstration in production environment and porting support to Aurix3G , (2021-2022) - Responsabile Scientifico
Commercial Research - Power Drop Aware NVM Concurrent BIST Test Strategies enabling Minimal Pincount FE Insertion (U-RPC) , (2019-2020) - Responsabile Scientifico
Commercial Research - Redundancy repair algorithm definition for A3G ESF3 based on Array Fail Diagnostic and Suspect Learning , (2019-2020) - Responsabile Scientifico
Commercial Research - New techniques for supporting the System-Level Test (SLT) phase fors automotive decives , (2019-2020) - Responsabile Scientifico
Commercial Research - Portable Repair DfM Approach for A2G/A3G Flash Test , (2019-2019) - Responsabile Scientifico
Commercial Research - Zynq MPSoC Ultrascale +(16nm generation) and Versal (7nm generation) , (2019-2020) - Responsabile Scientifico
Commercial Research - Zynq MPSoC Ultrascale +(16nm generation) , (2018-2019) - Responsabile Scientifico
Commercial Research - Portable Repari DfM Approach for A2G/A3G Flash Test , (2018-2019) - Responsabile Scientifico
Commercial Research - Everest and Alto projects , (2017-2018) - Responsabile Scientifico
Commercial Research - Concept and Implementation Guidelines for Test Time and Diagnosis – Optimal Usage of Hier-archical Design for Testability Hardware regarding typical Production Test Repair corner case Statistics , (2017-2017) - Responsabile Scientifico
Commercial Research - LPD (Low Powder Domain) subystem of the MPSoC device , (2017-2017) - Responsabile Scientifico
Commercial Research - LPD (Low Powder Domain) subystem of the MPSoC device , (2016-2017) - Responsabile Scientifico
Commercial Research - Assesment and Optimization of Hierarchical CPU-based Test for MultiCore eFlash applying DfT Hardware , (2016-2019) - Responsabile Scientifico
Commercial Research - SW BIST implementation for Floating Point Unit of 40nm Automotive Microcontrollers , (2016-2016) - Responsabile Scientifico
Consulting - Rinnovo della Convenzione Dipartimentale tra il Politecnico di Torino - Dipartimento di Automatica e Informatica (DAUIN), il Centre National de la Recherche Scientifique (CNRS) e l’Université de Montpellier (UM), riguardante il laboratorio franco-italiano per la ricerca in sistemi integrati hardware-software “LIA LAFISI” , (-2020) - Responsabile Scientifico
Departmental agreements - Everest and Alto projects , (-2018) - Responsabile Scientifico
Commercial Research
Supervised PhD students
- Nicola Di Gruttola Giardino. Programme in Ingegneria Aerospaziale (cycle 40, 2024-in progress)
Research subject: Enhancing Reliability and Autonomy of Miniaturized Deep-Space Avionic Systems, focusing on Planetary Robotic Platforms
Concurrent Engineering / Aerospace Systems Engineering - Lorenzo Cardone. Programme in Ingegneria Informatica E Dei Sistemi (cycle 38, 2022-in progress)
Research subject: Parallel Techniques for Reliability Measures
Computer architectures and Computer aided design Parallel and distributed systems, Quantum computing - Gabriele Filipponi. Programme in Ingegneria Informatica E Dei Sistemi (cycle 38, 2022-2026)
Thesis: Manufacturing and In-Field Testing Techniques
Computer architectures and Computer aided design - Tommaso Foscale. Programme in Ingegneria Informatica E Dei Sistemi (cycle 38, 2022-in progress)
Thesis: Testing Techniques for Automotive Systems on Chip
Computer architectures and Computer aided design - Nima Kolahimahmoudi. Programme in Ingegneria Informatica E Dei Sistemi (cycle 38, 2023-in progress)
Research subject: Functional Safety Techniques for Automotive oriented Systems-on-Chip
Computer architectures and Computer aided design - Francesco Angione. Programme in Ingegneria Informatica E Dei Sistemi (cycle 37, 2021-2025)
Thesis: System-Level Test techniques for Automotive SoCs
Computer architectures and Computer aided design Controls and system engineering Software engineering and Mobile computing - Giusy Iaria. Programme in Ingegneria Informatica E Dei Sistemi (cycle 37, 2022-2025)
Thesis: Towards Ultra-Reliable Automotive Systems-on-Chip
Computer architectures and Computer aided design - Giorgio Insinga. Programme in Ingegneria Informatica E Dei Sistemi (cycle 37, 2021-2025)
Thesis: Test and diagnosis of memories embedded in Automotive SoCs
Computer architectures and Computer aided design
Publications
Last years publications
Works published during the Ph.D. View all publications in Porto@Iris
- Bernardi, Paolo; Sterpone, Luca; Violante, Massimo; M., PORTELA GARCIA (2006)
HYBRID FAULT DETECTION TECHNIQUE A CASE STUDY ON VIRTEX-II PRO'S POWERPC. In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE, vol. 53, pp. 3550-3557. ISSN 0018-9499
Contributo su Rivista - Bernardi, Paolo; Grosso, Michelangelo; Rebaudengo, Maurizio; SONZA REORDA, Matteo (2006)
A pattern ordering algorithm for reducing the size of fault dictionaries. In: IEEE VLSI Test Symposium VTS, Berkeley, CA, USA, 30 Aprile - 4 Maggio 2006, pp. 166-171
Contributo in Atti di Convegno (Proceeding) - Bernardi, Paolo; VEIRAS BOLZANI, Leticia Maria; Rebaudengo, Maurizio; SONZA REORDA, ... (2006)
A new hybrid fault detection technique for systems-on-a-chip. In: IEEE TRANSACTIONS ON COMPUTERS, vol. 55, pp. 185-198. ISSN 0018-9340
Contributo su Rivista - Bernardi, Paolo; SANCHEZ SANCHEZ, EDGAR ERNESTO; Schillaci, Massimiliano; Squillero, ... (2006)
An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs. In: IEEE DATE 2006: Design, Automation and Test in Europe, 6-10 March 2006, pp. 412-417. ISBN: 9783981080100
Contributo in Atti di Convegno (Proceeding) - Bernardi, Paolo; Grosso, Michelangelo (2006)
Test Considerations about the Structured ASIC Paradigm. In: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems DDECS, Prague, Czech Republic, 18-21 Aprile 2006, pp. 230-231
Contributo in Atti di Convegno (Proceeding) - Appello, D; Bernardi, Paolo; Grosso, Michelangelo; SONZA REORDA, Matteo (2006)
System-in-package testing: problems and solutions. In: IEEE DESIGN & TEST OF COMPUTERS, vol. Volume: 23 , Issue: 3, pp. 203-211. ISSN 0740-7475
Contributo su Rivista - D., Appello; Bernardi, Paolo; Grosso, Michelangelo; Rebaudengo, Maurizio; SONZA REORDA, ... (2006)
On the automation of the test flow of complex SoCs. In: IEEE VLSI Test Symposium VTS, Berkeley, CA, USA, 30 Aprile - 4 Maggio 2006, pp. 386-391
Contributo in Atti di Convegno (Proceeding) - Bernardi, Paolo; VEIRAS BOLZANI, Leticia Maria; Violante, Massimo; SONZA REORDA, Matteo; ... (2006)
Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications. In: ?Congresso?
Contributo in Atti di Convegno (Proceeding) - Appello, D; Bernardi, Paolo; Grosso, Michelangelo; Rebaudengo, Maurizio; SONZA REORDA, ... (2006)
Embedded Memory Diagnosis: An Industrial Workflow. In: IEEE International Test Conference ITC, Santa Clara, CA, USA, 24-26 Ottobre 2006, pp. 1-9. ISBN: 9781424402922
Contributo in Atti di Convegno (Proceeding) - Bernardi, Paolo; SANCHEZ SANCHEZ, EDGAR ERNESTO; Schillaci, Massimiliano; SONZA REORDA, ... (2006)
An Evolutionary Methodology to Enhance Processor Software-Based Diagnosis. In: CEC 2006, IEEE Congress on Evolutionary Computation, Vancouver (BC), Canada, July 16-21, 2006, pp. 859-864
Contributo in Atti di Convegno (Proceeding) - Bernardi, Paolo; Grosso, Michelangelo; Rebaudengo, Maurizio; SONZA REORDA, Matteo (2005)
Exploiting an I-IP for both test and silicon debug of microprocessor cores. In: International Workshop on Microprocessor Test and Verification MTV, Austin, TX, USA, 3-4 Novembre 2005, pp. 55-62
Contributo in Atti di Convegno (Proceeding) - Bernardi, Paolo; VEIRAS BOLZANI, Leticia Maria; Rebaudengo, Maurizio; SONZA REORDA, ... (2005)
An integrated approach for increasing the soft-error detection capabilities in SoCs processors. In: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 307-312
Contributo in Atti di Convegno (Proceeding) - Bernardi, Paolo; Veiras Bolzani, Leticia Maria; Rebaudengo, Maurizio; Sonza Reorda, ... (2005)
On-line Detection of Control-Flow Errors in SoCs by means of an Infrastructure IP core. In: IEEE Dependable Systems and Networks Symposium, pp. 50-58
Contributo in Atti di Convegno (Proceeding) - Bernardi, Paolo; Grosso, Michelangelo; Rebaudengo, Maurizio; SONZA REORDA, Matteo (2005)
On the diagnosis of SoCs including multiple memory cores. In: IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Sopron, Hungary, 13-16 Aprile, 2005, pp. 75-80
Contributo in Atti di Convegno (Proceeding) - Bernardi, Paolo; Grosso, Michelangelo; Rebaudengo, Maurizio; SONZA REORDA, Matteo; D., ... (2005)
A Tool for Supporting and Automating the Test of Complex System-on-Chips. In: ITSW 2005: IEEE International Test Synthesis Workshop, San Antonio, Texas, USA, 11-12 aprile 2005
Contributo in Atti di Convegno (Proceeding) - D., Appello; Bernardi, Paolo; Grosso, Michelangelo; Rebaudengo, Maurizio; SONZA REORDA, ... (2005)
A new DFM-proactive technique. In: SDD'05: 2nd IEEE International Workshop on Silicon Debug and Diagnosis, Austin, Texas, USA, 10 - 11 novembre 2005
Contributo in Atti di Convegno (Proceeding) - Bernardi, Paolo; SANCHEZ SANCHEZ, EDGAR ERNESTO; Schillaci, Massimiliano; SONZA REORDA, ... (2005)
Diagnosing faulty functional units in processors by using automatically generated test sets. In: Sixth International Workshop on Microprocessor Test and Verification, 2005. MTV '05, Austin, TX (USA), 3-5 Nov. 2005. ISBN: 0769526276
Contributo in Atti di Convegno (Proceeding) - Bernardi, Paolo; VEIRAS BOLZANI, Leticia Maria; Rebaudengo, Maurizio; SONZA REORDA, ... (2005)
Pandora I-IP: an HW/SW approach to Control Flow Checking. In: 6th IEEE Latin American Test Workshop - LATW'05, Bahia Brazil, March 30 - April 2
Contributo in Atti di Convegno (Proceeding) - Bernardi, Paolo; Grosso, Michelangelo; Rebaudengo, Maurizio; SONZA REORDA, Matteo (2005)
Exploiting an Infrastructure-IP to reduce memory diagnosis costs in SoCs. In: IEEE European Test Symposium, Tallinn, Estonia, 22-25 Maggio 2005, pp. 202-207
Contributo in Atti di Convegno (Proceeding) - Bernardi, Paolo; Masera, Guido; Quaglio, Federico; SONZA REORDA, Matteo (2005)
Testing logic cores using a BIST P1500 compliant approach: a case of study. In: Design, Automation and Test in Europe Conference and Exhibition (DATE2005), Munich, 7-11 Marzo 2005, pp. 228-233
Contributo in Atti di Convegno (Proceeding)
Society and Enterprise
Patents and other intellectual properties
- Software analisi qualità schede elettroniche. national and international Patent
Inventors: Paolo Bernardi Giorgio Insinga