• INGEGNERIA INFORMATICA E DEI SISTEMI, 2023/2024 (40. ciclo)
  Politecnico di TORINO
• INGEGNERIA INFORMATICA E DEI SISTEMI, 2022/2023 (39. ciclo)
  Politecnico di TORINO
• INGEGNERIA INFORMATICA E DEI SISTEMI, 2021/2022 (38. ciclo)
  Politecnico di TORINO
• INGEGNERIA INFORMATICA E DEI SISTEMI, 2020/2021 (37. ciclo)
  Politecnico di TORINO
• INGEGNERIA INFORMATICA E DEI SISTEMI, 2019/2020 (36. ciclo)
  Politecnico di TORINO
• INGEGNERIA INFORMATICA E DEI SISTEMI, 2018/2019 (35. ciclo)
  Politecnico di TORINO

• Collegio di Ingegneria Informatica, del Cinema e Meccatronica. Componente

Master of Science

• Synthesis and optimization of digital systems. A.A. 2010/11, INGEGNERIA INFORMATICA (COMPUTER ENGINEERING). Collaboratore del corso

• EDA - Electronic Design Automation

Projects funded by competitive calls

• SENSEI - Sensemaking for Scalable IoT Platforms with In-Situ Data-Analytics: A Software-to-Silicon Solution for Energy-Efficient Machine-Learning on Chip , (2017-2019) - Responsabile Scientifico
  Corporate-funded and donor-funded research

Projects funded by commercial contracts

• Sviluppo di strumenti di progettazione automatica per tecnologie di intelligenza artificiale su dispositivi mobili embedded ad alta efficienza energetica , (2020-2022) - Responsabile Scientifico
  Participation in expenses for research activity

• Erich Malan. Programme in Ingegneria Informatica E Dei Sistemi (cycle 38, 2022-in progress)
  Research subject: Distributed and Federated Learning over IoT networks
  
  Computer architectures and Computer aided design
  Computer architectures and Computer aided design
• Chen Xie. Programme in Ingegneria Informatica E Dei Sistemi (cycle 36, 2020-2024)
  Thesis: Synthesis of Smart & Intelligent Sensors
  
  Computer architectures and Computer aided design
  Software engineering and Mobile computing
  Computer architectures and Computer aided design
  Software engineering and Mobile computing

• H., Karimiyan; Calimera, Andrea; Macii, Alberto; Macii, Enrico; Poncino, Massimo (2011)
  An on-chip all-digital PV-monitoring architecture for digital IPs. In: 21st International Workshop on Power and Timing Modeling, Optimization, and Simulation, PATMOS 2011, Madrid (SP), September 26-29, 2011, pp. 162-172. ISSN 0302-9743
  Contributo in Atti di Convegno (Proceeding)
• Calimera, Andrea; M., Loghi; Macii, Enrico; Poncino, Massimo (2011)
  Buffering of frequent accesses for reduced cache aging. In: GLS-VLSI: ACM/IEEE Great Lakes Symposium on VLSI, 2011, pp. 295-300
  Contributo in Atti di Convegno (Proceeding)
• C., Ferri; D., Papagiannopoulou; R., Bahar; Calimera, Andrea (2011)
  NBTI-Aware Data Allocation Strategies for Scratchpad Memory Based Embedded Systems. In: LATW: IEEE Latin American Test Workshop, 2011, pp. 1-6
  Contributo in Atti di Convegno (Proceeding)
• S., Rinaudo; G., Gangemi; Calimera, Andrea; Macii, Alberto; Poncino, Massimo (2011)
  Moving to Green ICT: From stand-alone power-aware IC design to an integrated approach to energy efficient design for heterogeneous electronic systems. In: 14th Design, Automation and Test in Europe Conference and Exhibition, DATE 2011, Grenoble (FRA), 14-18 March 2011, pp. 1127-1128
  Contributo in Atti di Convegno (Proceeding)
• L. d., Lima; Calimera, Andrea; Macii, Alberto; Macii, Enrico; Poncino, Massimo (2011)
  Power Efficient Variability Compensation Through Clustered Tunable Power-Gating. In: IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, vol. 1, pp. 242-253. ISSN 2156-3357
  Contributo su Rivista
• F., Lavratti; Calimera, Andrea; L., Bolzani; F., Vargas; Macii, Enrico (2011)
  A New Built-In Current Sensor Scheme to Detect Dynamic Faults in Nano-Scale SRAMs. In: LATW: IEEE Latin American Test Workshop, 2011, pp. 1-6
  Contributo in Atti di Convegno (Proceeding)
• Calimera, Andrea; M., Loghi; Macii, Enrico; Poncino, Massimo (2011)
  Partitioned cache architectures for reduced NBTI-induced aging. In: DATE 2011, 2011, pp. 1-6
  Contributo in Atti di Convegno (Proceeding)
• Lingasubramanian, Karthikeyan; Calimera, Andrea; Macii, Alberto; Macii, Enrico; Poncino, ... (2011)
  Sub-row sleep transistor insertion for concurrent clock-gating and power-gating. In: 21st International Workshop on Power and Timing Modeling, Optimization, and Simulation, PATMOS 2011, Madrid (SP), September 26-29, 2011, pp. 214-225. ISSN 0302-9743
  Contributo in Atti di Convegno (Proceeding)
• Sassone, Alessandro; Liu, Wei; Calimera, Andrea; Macii, Alberto; Macii, Enrico; Poncino, ... (2011)
  Modeling of thermally induced skew variations in clock distribution network. In: 17th International Workshop on Thermal Investigations of ICs and Systems, THERMINIC 2011, Paris (FRA), 27-29 Sept. 2011, pp. 1-6
  Contributo in Atti di Convegno (Proceeding)
• M., Caldera; Calimera, Andrea; Macii, Alberto; Macii, Enrico; Poncino, Massimo (2010)
  Minimizing temperature sensitivity of dual-Vt CMOS circuits using Simulated-Annealing on ISING-like models. In: THERMINIC-2010: IEEE International Workshop on Thermal Investigations of ICs and Systems, Barcelona (ESP), October, pp. 189-194
  Contributo in Atti di Convegno (Proceeding)
• Calimera, Andrea; Macii, Enrico; Poncino, Massimo (2010)
  NBTI-Aware Clustered Power Gating. In: ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, pp. 3-1-3-25. ISSN 1084-4309
  Contributo su Rivista
• Acquaviva, Andrea; Calimera, Andrea; Macii, Alberto; Poncino, Massimo; Macii, Enrico; ... (2010)
  An integrated thermal estimation framework for industrial embedded platforms. In: GLSVLSI'10: Great Lakes Symposium on VLSI, Providence, Rhode Island, May 2010, pp. 293-298
  Contributo in Atti di Convegno (Proceeding)
• Calimera, Andrea; Bahar, R. I.; Macii, Enrico; Poncino, Massimo (2010)
  Dual-Vt Assignment Policies in ITD-Aware Synthesis. In: MICROELECTRONICS JOURNAL, vol. 41, pp. 547-553. ISSN 0959-8324
  Contributo su Rivista
• Calimera, Andrea; Macii, Enrico; Ravotto, Danilo; SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA ... (2010)
  Generating Power-Hungry Test Programs for Power-Aware Validation of Pipelined Processors. In: 23rd annual symposium on Integrated circuits and system design, São Paulo, Brazil, September 2010, pp. 61-66. ISBN: 9781450302883
  Contributo in Atti di Convegno (Proceeding)
• Liu, Wei; Nannarelli, A.; Calimera, Andrea; Macii, Enrico; Poncino, Massimo (2010)
  Post-placement temperature reduction techniques. In: DATE'10: IEEE Designa, Automation and Test in Europe, Dresden, March, pp. 634-637. ISBN: 9783981080162
  Contributo in Atti di Convegno (Proceeding)
• Calimera, Andrea; Macii, Alberto; Macii, Enrico; S., Rinaudo; Poncino, Massimo (2010)
  THERMINATOR: Modeling, control and management of thermal effects in electronic circuits of the future. In: THERMINIC-10: International Workshop on Thermal Investigations of ICs and Systems, Barcelona, October, pp. 171-176. ISBN: 9781424484539
  Contributo in Atti di Convegno (Proceeding)
• Calimera, Andrea; R., Bahar; Macii, Enrico; Poncino, Massimo (2010)
  Temperature-Insensitive Dual-Vth Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence. In: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, vol. 18, pp. 1608-1620. ISSN 1063-8210
  Contributo su Rivista
• Acquaviva, Andrea; Calimera, Andrea; Macii, Alberto; Poncino, Massimo; Macii, Enrico; ... (2010)
  An integrated thermal estimation framework for industrial embedded platforms.. In: ACM Great Lakes Symposium on VLSI 2010
  Contributo in Atti di Convegno (Proceeding)
• Calimera, Andrea; Macii, Enrico; Poncino, Massimo (2010)
  Analysis of NBTI-induced SNM degradation in power-gated SRAM cells. In: IEEE ISCAS-10: IEEE International Symposium on Circuits and Systems, May, pp. 785-788. ISBN: 9781424453085
  Contributo in Atti di Convegno (Proceeding)
• Wei, L.; Calimera, Andrea; Nannarelli, A.; Macii, Enrico; Poncino, Massimo (2010)
  On-chip Thermal Modeling Based on SPICE Simulation. In: 19th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2009, Delft (NL), September 9-11, 2009, pp. 66-75. ISSN 0302-9743. ISBN: 9783642118012
  Contributo in Atti di Convegno (Proceeding)

• Stima di profondità a ridotto consumo di potenza, e altri segnali da singola immagine. national and international Patent
  Inventors: Andrea Calimera Antonio Cipolletta Valentino Peluso