Ph.D. in Ingegneria Informatica E Dei Sistemi , 19th cycle (2004-2006)
Ph.D. obtained in 2007
Dissertation:
Electronic System Design Techniques for safety Critical Applications.
Tutors:
Matteo Sonza ReordaProfile
Research interests
Scientific branch
(Area 0009 - Industrial and information engineering)
Awards and Honors
Teaching
Collegi of the PhD programmes
- INGEGNERIA INFORMATICA E DEI SISTEMI, 2023/2024 (40. ciclo)
Politecnico di TORINO - INGEGNERIA INFORMATICA E DEI SISTEMI, 2022/2023 (39. ciclo)
Politecnico di TORINO - INGEGNERIA INFORMATICA E DEI SISTEMI, 2021/2022 (38. ciclo)
Politecnico di TORINO - INGEGNERIA INFORMATICA E DEI SISTEMI, 2020/2021 (37. ciclo)
Politecnico di TORINO - INGEGNERIA INFORMATICA E DEI SISTEMI, 2019/2020 (36. ciclo)
Politecnico di TORINO - INGEGNERIA INFORMATICA E DEI SISTEMI, 2018/2019 (35. ciclo)
Politecnico di TORINO - INGEGNERIA INFORMATICA E DEI SISTEMI, 2017/2018 (34. ciclo)
Politecnico di TORINO - INGEGNERIA INFORMATICA E DEI SISTEMI, 2016/2017 (33. ciclo)
Politecnico di TORINO - INGEGNERIA INFORMATICA E DEI SISTEMI, 2015/2016 (32. ciclo)
Politecnico di TORINO
Collegi of the degree programmes
Teaching and training projects
Projects funded by competitive calls
- Reinforcing Skills in Chips Design for Europe, (2024-2028) - Componente gruppo di Ricerca
University cooperation
Projects funded by commercial contracts
- Corso Python Base e Corso Python Advanced, (2022-2023) - Responsabile Scientifico
Commercial contracts - Phyton programming language training, (2020-2020) - Responsabile Scientifico
Commercial contracts
Other activities and projects related to teaching
The teaching activity of Luca Sterpone has been focused on three fundamental courses for the Bachelor degree (Laurea) in Computer Engineering: Computer Science, Computer Architecture and Operating Systems.
Luca Sterpone actively contributes to the innovation of the courses contents in particular promoting the adoption of state-of-the-art scripting language for the courses of Operating Systems and contributing to the adoption of modern MIPS architecture for the course of Computer Architecture. Besides, since the academic year 2014/2015, Luca Sterpone is formal responsible of the PhD course of Reconfigurable Computing whose content has been personally created and managed. The course is constantly updated with the research advancements in the area of reconfigurable computing and it has an average of 15 PhD students per academic year.
• Formal responsibility of Bachelor’s (Laurea) and Master of Science’s (Laurea Magistrale) degree courses in Italian and/or foreign universities
- Computer Science, Politecnico di Torino, Italian language, 9 years, (A.A. 2010/2011, 2011/2012, 2012/2013, 2013/2014, 2014/2015, 2015/2016, 2016/2017, 2017/2018, 2018/2019)
- Operating Systems, Politecnico di Torino, Italian language, 7 years (A.A. 2014/2015, 2015/2016, 2016/2017, 2017/2018, 2018/2019, 2019/2020, 2020/2021)
- Computer Architecture, Politecnico di Torino, Italian language, 3 years (A.A. 2018/2019, 2019/2020, 2020/2021)
• Formal responsibility of PhD courses in Italian and/or foreign universities.
- Reconfigurable Computing, English, 7 years (A.A. 2014/2015, 2015/2016, 2016/2017, 2017/2018, 2018/2019, 2019/2020, 2020/2021)
Research
Research groups
Research projects
Projects funded by competitive calls
- PUMA - develoPpement of a rad-hard fpga with Ultra deep subMicron technology for spAce applications , (2025-2027) - Responsabile Scientifico
UE-funded research - HE - Global Challenges - Digital, Industry and Space - REASE: REsilient computing Architecture in the Space quantum communication Era , (2023-2025) - Responsabile Scientifico
Nationally funded research - PRIN - NODES - Spoke 1 - Nord Ovest Digitale E Sostenibile - INDUSTRY 4.0 FOR SUSTAINABLE MOBILITY AND AEROSPACE (Spoke 1) , (2022-2025) - Responsabile Scientifico di Struttura
PNRR – Mission 4 - VEGAS - COMPET-01-2015 , (2016-2018) - Responsabile Scientifico
UE-funded research - H2020 - Industrial Leadership – LEIT - SPACE
Projects funded by commercial contracts
- RAMSES CubeSat-1 Development , (2025-2026) - Responsabile Scientifico
Commercial Research - Design Mitigation Techniques Evaluation of Advanced COTS FPGAS for ESA Missions , (2024-2026) - Responsabile Scientifico
Commercial Research - Digital Model of a High Integrity Avionic Backbone , (periodo sconosciuto) - Responsabile Scientifico
Commercial Research - Contratto di ricerca tra Politecnico di Torino (DAUIN) e ARGOTEC S.R.L. Società Unipersonale per lo svolgimento del programma di ricerca dal titolo: “EuFRATE European FPGA Radiation-hardened Architecture for TElecommunications”. , (periodo sconosciuto) - Responsabile Scientifico
Commercial Research - FPL 2024 , (2024-2024) - Responsabile Scientifico
Sponsorship - FPL 2024 , (2024-2024) - Responsabile Scientifico
Sponsorship - FPL 2024 , (2024-2024) - Responsabile Scientifico
Sponsorship - FPL 2024 , (2024-2024) - Responsabile Scientifico
Sponsorship - High Integrity Avionic Backbone , (2024-2024) - Responsabile Scientifico
Commercial Research - DFVC integr. x AC motor on uC Infineon , (2024-2024) - Responsabile Scientifico
Commercial Research - Studio e investigazione dell'ambiente radioattivo relativo alla missione RAMSES, definizione di requisiti di test di dispositivi, supporto al tailoring ECSS , (2024-2024) - Responsabile Scientifico
Commercial Research - TERRAC: Towards Exascale Reconfigurable and Rad-hard Accelerated Computing in Space , (2023-2024) - Responsabile Scientifico
Commercial Research - Attività di supporto e consulenza in relazione alle attività di radiation analysis and mitigation dell’FPGA dell’F-DCU , (2023-2024) - Responsabile Scientifico
Consulting - DEV.of Electronic Power Conv.for , (2023-2024) - Responsabile Scientifico
Commercial Research - Sperimentazioni, revisioni e test sul processore tollerante ai guasti Rempro , (2022-2023) - Responsabile Scientifico
Commercial Research - Python Basics , (2021-2021) - Responsabile Scientifico
Commercial Research - Attività di Integrazione IP cores in FPGA , (2020-2020) - Responsabile Scientifico
Commercial Research - Attività di supporto per test di radiazioni (ioni pesanti)” , (2020-2020) - Responsabile Scientifico
Commercial Research - Phyton programming language training , (2018-2019) - Responsabile Scientifico
Commercial Research - Developement of New Place and Route Tools to improve Set Mitigation in ACTEL ProASIC FPGA , (2018-2019) - Responsabile Scientifico
Commercial Research - Disrupting vehicle controls and fleet management: block-chain, parallel computing and quantum computing , (2018-2019) - Responsabile Scientifico
Commercial Research - Development of software testing framework with a Virtual Hardware prototyping tool , (2018-2019) - Responsabile Scientifico
Commercial Research - Radiation test on SmartFusion2 FPGA , (2018-2018) - Responsabile Scientifico
Commercial Research - SEE analysis and mitigation on SRAM and Flash-based FPGAs , (2017-2018) - Responsabile Scientifico
Commercial Research - Design including definition of inputs, SW testing setup, Hardware Integration and Final release of the FW and documents , (2017-2017) - Responsabile Scientifico
Commercial Research - FPGA base test and Complex Driver , (2016-2016) - Responsabile Scientifico
Commercial Research - Development of new place and route tools to improve SET mitigation in Actel ProASIC FPGAs , (2015-2016) - Responsabile Scientifico
Commercial Research
Supervised PhD students
- Arash Amini Bardpareh. Programme in Ingegneria Informatica E Dei Sistemi (cycle 40, 2025-in progress)
- Federico Buccellato. Programme in Ingegneria Informatica E Dei Sistemi (cycle 40, 2024-in progress)
Research subject: High-End AI-Enhanced Computing System for Space Application
Computer architectures and Computer aided design Data science, Computer vision and AI Parallel and distributed systems, Quantum computing Software engineering and Mobile computing Computer architectures and Computer aided design Data science, Computer vision and AI Parallel and distributed systems, Quantum computing Software engineering and Mobile computing - Aobo Cui. Programme in Ingegneria Informatica E Dei Sistemi (cycle 40, 2025-in progress)
- Giorgio Cora. Programme in Ingegneria Informatica E Dei Sistemi (cycle 39, 2023-in progress)
Research subject: Resilient computing architecture in the space quantum communication era
Computer architectures and Computer aided design Computer architectures and Computer aided design - Rosario Milazzo. Programme in Ingegneria Informatica E Dei Sistemi (cycle 38, 2023-in progress)
Data science, Computer vision and AI Data science, Computer vision and AI Data science, Computer vision and AI - Andrea Portaluri. Programme in Ingegneria Informatica E Dei Sistemi (cycle 37, 2021-in progress)
Thesis: AI-oriented Design Methods for Intelligent Aerospace Computing Systems - Eleonora Vacca. Programme in Ingegneria Informatica E Dei Sistemi (cycle 37, 2021-2025)
Thesis: Reconfigurable Accelerators Design Methods for High Reliability Space Applications
Computer architectures and Computer aided design - Corrado De Sio. Programme in Ingegneria Informatica E Dei Sistemi (cycle 35, 2019-2023)
Thesis: Toward Fault-Tolerant Applications on Reconfigurable Systems-on-Chip
Controls and system engineering Cybersecurity Controls and system engineering Cybersecurity
Other activities and projects related to research
Publications
PoliTO co-authors
Last years publications
Publications by type
Works published during the Ph.D. View all publications in Porto@Iris
- S., Pontarelli; Sterpone, Luca; G. C., Cardarilli; M., Re; SONZA REORDA, Matteo; A., ... (2007)
Optimization of Self Checking FIR filters by means of Fault Injection Analysis. In: DFT, Roma, pp. 96-104
Contributo in Atti di Convegno (Proceeding) - Sterpone, Luca; Violante, Massimo; HARBOE SORENSEN, R; Merodio, D; Sturesson, F; ... (2007)
Experimental Validation of a Tool for Predicting the Effects of Soft Errors in SRAM-based FPGAs. In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE, vol. 6, pp. 2576-2583. ISSN 0018-9499
Contributo su Rivista - Sterpone, Luca; Violante, Massimo (2007)
Static and Dynamic Analysis of SEU effects in SRAM-based FPGAs. In: ETS2007: IEEE European Test Symposium, Freiburg, Germany, 2007, Freiburg, Germany, May 20-24. 2007.
Contributo in Atti di Convegno (Proceeding) - Sterpone, Luca; Violante, Massimo (2007)
A new FPGA-based edge detection system for the gridding of DNA microarray images. In: IEEE Instrumentation and Measurement Technology Conference, Warsaw., May 1-3, 2007
Contributo in Atti di Convegno (Proceeding) - Abate, F.; Sterpone, Luca; Violante, Massimo (2007)
A new mitigation approach for soft errors in embedded processors. In: Radiation and Its Effects on Components and Systems, 2007. RADECS 2007. 9th European Conference on. ISBN: 9781424417049
Contributo in Atti di Convegno (Proceeding) - Sterpone, Luca; Violante, Massimo (2007)
An Analysis of SEU Effects in Embedded Operating Systems for Real-Time Applications. In: International Symposium on Industrial Electronics, pp. 3345-3349. ISBN: 9781424407552
Contributo in Atti di Convegno (Proceeding) - Sterpone, Luca; Violante, Massimo (2007)
A new hardware architecture for performing the gridding of DNA microarray images. In: ACM 17th Great Lake Symposium on VLSI, Stresa., March 11-13, 2007.
Contributo in Atti di Convegno (Proceeding) - Sterpone, Luca; Violante, Massimo (2007)
A new decompression system for the configuration process of SRAM-based FPGAs. In: ACM 17th Great Lake Symposium on VLSI, Stresa., March 11-13, 2007
Contributo in Atti di Convegno (Proceeding) - Manuzzato, A; Rech, P; Gerardin, S; Paccagnella, A; Sterpone, Luca; Violante, Massimo (2007)
Sensitivity evaluation of TMR-hardened circuits to multiple SEUs induced by alpha particles in commercial SRAM-based FPGAs. In: International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 79-86
Contributo in Atti di Convegno (Proceeding) - Alderighi, M.; Casini, F.; D'Angelo, S.; Mancini, M.; Pastore, S.; Sterpone, Luca; ... (2007)
Soft errors in SRAM-FPGAs: A comparison of two complementary approaches. In: Radiation and Its Effects on Components and Systems, 2007. RADECS 2007. 9th European Conference on. ISBN: 9781424417049
Contributo in Atti di Convegno (Proceeding) - Sterpone, Luca; Violante, Massimo (2007)
Analytical analysis of the MCUs sensitiveness of TMR architectures in SRAM-based FPGAs. In: Radiation and Its Effects on Components and Systems, 2007. RADECS 2007. 9th European Conference on. ISBN: 9781424417049
Contributo in Atti di Convegno (Proceeding) - Sterpone, Luca; Violante, Massimo (2007)
A New Partial Reconfiguration-based Fault-Injection System to Evaluate SEU Effects in SRAM-based FPGAs. In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE, pp. 965-970. ISSN 0018-9499
Contributo su Rivista - Manuzzato, A.; Gerardin, S.; Paccagnella, A.; Sterpone, Luca; Violante, Massimo (2007)
Effectiveness of TMR-based techniques to mitigate alpha-induced SEU accumulation in commercial SRAM-based FPGAs. In: Radiation and Its Effects on Components and Systems, 2007. RADECS 2007. 9th European Conference on. ISBN: 9781424417049
Contributo in Atti di Convegno (Proceeding) - Violante, Massimo; SONZA REORDA, Matteo; Sterpone, Luca; Manuzzato, A.; Gerardin, S.; ... (2007)
A new hardware/software platform for the soft-error sensitivity evaluation of FPGA devices. In: 8th IEEE Latin American Test Workshop, Cuzco, Peru, pp. 1-6
Contributo in Atti di Convegno (Proceeding) - Violante, Massimo; Sterpone, Luca; Manuzzato, A; Gerardin, S; Rech, P; Bagatin, M; ... (2007)
A new hardware/software platform and a new 1/E neutron source for soft error studies: testing FPGAs at the ISIS facility. In: IEEE TRANSACTIONS ON NUCLEAR SCIENCE, pp. 1184-1189. ISSN 0018-9499
Contributo su Rivista - S., Pontarelli; Sterpone, Luca; G. C., Cardarilli; M., Re; SONZA REORDA, Matteo; A., ... (2007)
Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders. In: IOLTS2007: IEEE International On-Line Testing Symposium, Hersonissos, Greece, July 2007, pp. 194-196
Contributo in Atti di Convegno (Proceeding) - Sterpone, Luca; P., REYES MORENO; J. A., Maestro; O., Ruano; P., Reviriego (2007)
An experimental analysis of SEU sensitiveness of recursive-oriented hardening techniques. In: DDECS2007: IEEE Design & Diagnostic of Electronic Circuits & Systems, 2007, Krakow, Poland, April 11,13. 2007
Contributo in Atti di Convegno (Proceeding) - SONZA REORDA, Matteo; Sterpone, Luca; Violante, Massimo; LIMA KASTENSMIDT, F; Carro, L. (2007)
Evaluating different solutions to design fault tolerant systems with SRAM-based FPGAs. In: JOURNAL OF ELECTRONIC TESTING, vol. 23, pp. 47-54. ISSN 0923-8174
Contributo su Rivista - Rebaudengo, Maurizio; Sterpone, Luca; Violante, Massimo; C., Bolchini; A., Miele; D., ... (2006)
Combined software and hardware techniques for the design of reliable IP processors. In: 21th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 265-273
Contributo in Atti di Convegno (Proceeding) - Martina, Maurizio; Masera, Guido; Molino, Andrea; Vacca, Fabrizio; Sterpone, Luca; ... (2006)
A new approach to compress the configuration information of programmable devices. In: DATE, Monaco di Baviera, 6-10 marzo 2006, pp. 1289-1293
Contributo in Atti di Convegno (Proceeding)
Society and Enterprise
Patents and other intellectual properties
- Pyxel – A Python Toolkit For Automating Research, Development, And Analysis On Reconfigurable Hardware. national Software
Inventors: Sarah Azimi Corrado De Sio Luca Sterpone - Reliability assessment in FPGAs based on Critical Bits identification. international Patent
Inventors: Luca Sterpone - SOFTWARE FOR EXPLOITING SURVEILLANCE VIDEOS FOR REAL-TIME DETECTION OF VIOLENCE THROUGH "SIGNAL FOR HELP". national Software
Inventors: Sarah Azimi Francesco Carlucci Corrado De Sio Luca Sterpone