Eco-Algoritmi, risparmio di energia nei data centers

Corso di laurea magistrale

• Modeling and optimization of embedded systems. A.A. 2022/23, INGEGNERIA INFORMATICA (COMPUTER ENGINEERING). Collaboratore del corso

• Bosio, Roberto; Brignone, Giovanni; Minnella, Filippo; Jamal, MUHAMMAD USMAN; Lavagno, ... (2024)
  LESS: Low-Power Energy-Efficient Subgraph Isomorphism on FPGA. In: 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), Valencia (Spain), 25-27 March 2024, pp. 1-2. ISBN: 978-3-9819263-8-5
  Contributo in Atti di Convegno (Proceeding)
• Minnella, Filippo (2024)
  Mix & Latch: High-Performance Designs with Single-Clock Mixed-Polarity Latches and Flip-Flops. relatore: LAVAGNO, Luciano; LAZARESCU, MIHAI TEODOR; , 36. XXXVI Ciclo, P.: 66
  Doctoral Thesis
• Lagostina, Lorenzo; Minnella, Filippo; Cortadella, Jordi; Casu, Mario R.; Lazarescu, ... (2024)
  Mix & Latch: Comparison With State-of-the-Art Retiming On a RISC-V Benchmark. In: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, vol. 43, pp. 2229-2233. ISSN 0278-0070
  Contributo su Rivista
• Minnella, Filippo; Cortadella, Jordi; Casu, Mario R.; Lazarescu, Mihai T.; Lavagno, ... (2023)
  Mix & Latch: An Optimization Flow for High-Performance Designs with Single-Clock Mixed-Polarity Latches and Flip-Flops. In: IEEE ACCESS, vol. 11, pp. 1-1. ISSN 2169-3536
  Contributo su Rivista
• Minnella, Filippo (2022)
  Electronic device comprising a memory accessible via a JTAG interface, and corresponding method of accessing a memory. N. brevetto: US11789078B2, propr. brevetto: 4 - Soggetti terzi
  Brevetti

• MIx&Latch: a method to increase the operating frequency of synchronous digital circuits using a single clock tree and a mixed distribution of sequential elements. Brevetto nazionale e internazionale
  Inventori: Mario Roberto Casu Luciano Lavagno Filippo Minnella