Ph.D. in Ingegneria Elettrica, Elettronica E Delle Comunicazioni , 36th cycle (2020-2023)
Ph.D. obtained in 2024
Dissertation:
Mix & Latch: High-Performance Designs with Single-Clock Mixed-Polarity Latches and Flip-Flops (Abstract)
Tutors:
Luciano Lavagno Mihai Teodor LazarescuProfile
Research topic
Eco-Algorithms. Energy saving in data centers
Research interests
Biography
After that I decided to enroll for the Master degree in Electronics Engineering choosing a curriculum that focuses mainly in Embedded Systems applications.
Thanks to second level courses, I had the chance to experience different digital architectures, to acquire knowledge related to digital design and synthesis, and to collaborate with different students in order to develop specific projects.
I developed the Master thesis in the framework of the Inner Tracking System update at CERN, the goal was to obtain a radiation hardened soft-core for specific FPGA devices. After that, I graduated in April 2018.
Here is a link to the thesis pdf file: https://webthesis.biblio.polito.it/7536/1/tesi.pdf.
From February 2018 to October 2020 I worked as digital designer for STMicroelectronics Powertrain and Safety division; here I was able to deepen my knowledge regarding ASIC design and verification, experiencing different automotive applications and learning industrial standards for devices development and safety requirements.
Starting from November 2020 I am working as PhD student for Politecnico di Torino doctoral program in Electrical, Electronics and Communications Engineering.
The object of this PhD is to explore state of the art solutions in terms of energy saving for data centers and to find new algorithms and architectures able to reach this goal.
Teaching
Teachings
Master of Science
- Modeling and optimization of embedded systems. A.A. 2022/23, INGEGNERIA INFORMATICA (COMPUTER ENGINEERING). Collaboratore del corso
Publications
Works published during the Ph.D. View all publications in Porto@Iris
- Lagostina, Lorenzo; Minnella, Filippo; Cortadella, Jordi; Casu, Mario R.; Lazarescu, ... (2024)
Mix & Latch: Comparison With State-of-the-Art Retiming On a RISC-V Benchmark. In: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, vol. 43, pp. 2229-2233. ISSN 0278-0070
Contributo su Rivista - Minnella, Filippo (2024)
Mix & Latch: High-Performance Designs with Single-Clock Mixed-Polarity Latches and Flip-Flops. relatore: LAVAGNO, Luciano; LAZARESCU, MIHAI TEODOR; , 36. XXXVI Ciclo, P.: 66
Doctoral Thesis - Bosio, Roberto; Brignone, Giovanni; Minnella, Filippo; Jamal, MUHAMMAD USMAN; Lavagno, ... (2024)
LESS: Low-Power Energy-Efficient Subgraph Isomorphism on FPGA. In: 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), Valencia (Spain), 25-27 March 2024, pp. 1-2. ISBN: 978-3-9819263-8-5
Contributo in Atti di Convegno (Proceeding) - Minnella, Filippo; Cortadella, Jordi; Casu, Mario R.; Lazarescu, Mihai T.; Lavagno, ... (2023)
Mix & Latch: An Optimization Flow for High-Performance Designs with Single-Clock Mixed-Polarity Latches and Flip-Flops. In: IEEE ACCESS, vol. 11, pp. 1-1. ISSN 2169-3536
Contributo su Rivista - Minnella, Filippo (2022)
Electronic device comprising a memory accessible via a JTAG interface, and corresponding method of accessing a memory. N. brevetto: US11789078B2, propr. brevetto: 4 - Soggetti terzi
Brevetti