Dottorato in Ingegneria Informatica E Dei Sistemi , 26o ciclo (2011-2013)
Dottorato concluso nel 2014
Tesi:
CAD Solutions for Non Silicon Nano Electronic Circuits and Systems
Tutori:
Enrico MaciiPubblicazioni
Pubblicazioni più recenti Vedi tutte le pubblicazioni su Porto@Iris
- Conti, Elia; Barbero, Marlon; Fougeron, Denis; Godiot, Stephanie; Menouni, Mohsine; ... (2018)
Development of a Large Pixel Chip Demonstrator in RD53 for ATLAS and CMS Upgrades. In: POS PROCEEDINGS OF SCIENCE, vol. TWEPP-17. ISSN 1824-8039
Contributo su Rivista - Rizzo, ROBERTO GIORGIO; Miryala, Sandeep; Calimera, Andrea; Macii, Enrico; Poncino, ... (2015)
Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions.. In: GLSVLSI '15, Pittsburgh, PA (USA), 20-22 May, pp. 253-258. ISBN: 978-1-4503-3474-7
Contributo in Atti di Convegno (Proceeding) - Miryala, Sandeep; Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo; ... (2015)
Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization. In: Great Lakes Symposium on VLSI, pp. 39-44. ISBN: 9781450334747
Contributo in Atti di Convegno (Proceeding) - Miryala, Sandeep; Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, Massimo (2015)
Ultra-low power circuits using graphene p-n junctions and adiabatic computing. In: MICROPROCESSORS AND MICROSYSTEMS, vol. 39, pp. 962-972. ISSN 0141-9331
Contributo su Rivista - Miryala, Sandeep; Calimera, Andrea; Macii, Enrico; Poncino, Massimo (2014)
Ultra Low-Power Computation via Graphene-Based Adiabatic Logic Gates. In: DSD-14: IEEE Euromicro Conference on Digital System Design, pp. 365-371
Contributo in Atti di Convegno (Proceeding) - Miryala, Sandeep; M., Oleiro; L., Bolzani Pohls; Calimera, Andrea; Macii, Enrico; ... (2014)
Modeling of Physical Defects in PN-Junction Based Graphene Devices. In: JOURNAL OF ELECTRONIC TESTING, vol. 30, pp. 357-370. ISSN 0923-8174
Contributo su Rivista - Miryala, Sandeep (2014)
CAD Solutions for Graphene Based Nanoelectronic Circuits and Systems. relatore: Enrico Macii, 26. XXVI, P.: 109
Doctoral Thesis - Tenace, Valerio; Miryala, Sandeep; Calimera, Andrea; Macii, Alberto; Macii, Enrico; ... (2014)
Row-Based Body-Bias Assignment for Dynamic Thermal Clock-Skew Compensation. In: MICROELECTRONICS JOURNAL, vol. 45, pp. 530-538. ISSN 0959-8324
Contributo su Rivista - Baljit, Kaur; Miryala, Sandeep; S. K., Manhas; Bulusu, Anand (2013)
An efficient method for ECSM characterization of CMOS inverter in nanometer range technologiesInternational Symposium on Quality Electronic Design (ISQED). In: International Symposium on Quality Electronic Design (ISQED), pp. 665-669. ISBN: 9781467349512
Contributo in Atti di Convegno (Proceeding) - Miryala, Sandeep; Calimera, Andrea; Macii, Enrico; Poncino, Massimo (2013)
Power Modeling and Characterization of Graphene-Based Logic Gates. In: PATMOS-13: IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation, Karlsruhe, September, pp. 223-226
Contributo in Atti di Convegno (Proceeding) - Miryala, Sandeep; Calimera, Andrea; Macii, Enrico; Poncino, Massimo (2013)
Exploration of different implementation styles for graphene-based reconfigurable gates. In: ICICDT-13: IEEE International Conference on IC Design & Technology, Pavia, May, pp. 21-24
Contributo in Atti di Convegno (Proceeding) - Miryala, Sandeep; Calimera, Andrea; Macii, Enrico; Poncino, Massimo; Bolzani, L. (2013)
Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices. In: LATW-13: IEEE Latin American Test Workshop, Cordoba, April, pp. 1-6
Contributo in Atti di Convegno (Proceeding) - Miryala, Sandeep; Calimera, Andrea; Macii, Enrico; Poncino, Massimo (2013)
Delay model for reconfigurable logic gates based on graphene PN-junctions. In: GLSVLSI-13: ACM Great Lakes Symposium on VLSI, Paris, May, pp. 227-232
Contributo in Atti di Convegno (Proceeding) - Miryala, Sandeep; Montazeri, M.; Calimera, Andrea; Macii, Enrico; Poncino, Massimo (2013)
A Verilog-A Model for Reconfigurable Logic Gates Based on Graphene pn-Junctions. In: DATE-13: ACM/IEEE Design, Automation & Test in Europe, Dresden, March, pp. 877-880
Contributo in Atti di Convegno (Proceeding) - Tenace, Valerio; Miryala, Sandeep; Calimera, Andrea; Macii, Alberto; Macii, Enrico; ... (2012)
Layout Constrained Body-Biasing for Temperature Induced Clock-Skew Compensation. In: THERMINIC-12: IEEE International Workshop on Thermal Investigations of ICs and Systems, Budapest, September, pp. 1-6
Contributo in Atti di Convegno (Proceeding) - Wei, L.; Miryala, Sandeep; Tenace, Valerio; Calimera, Andrea; Macii, Enrico; Poncino, ... (2012)
NBTI effects on tree-like clock distribution networks. In: GLSVLSI-12: IEEE/ACM Great Lakes symposium on VLSI, Salt Lake City, Utah, May 2012, pp. 279-282. ISBN: 9781450312448
Contributo in Atti di Convegno (Proceeding) - Miryala, Sandeep; Calimera, Andrea; Macii, Enrico; Poncino, Massimo (2012)
IR-Drop Analysis of Graphene-Based Power Distribution Networks. In: DATE-12: IEEE Design Automation and Test in Europe, Dresden, Germany, March 2012, pp. 81-86. ISBN: 9781457721458
Contributo in Atti di Convegno (Proceeding)