Giusy Iaria

Ph.D. in Ingegneria Informatica E Dei Sistemi , 37^th cycle (2021-2024)

Ph.D. obtained in 2025

Profile

Research topic

Towards Ultra-Reliable Automotive Systems-on-Chip

Research interests

Computer architectures and Computer aided design

Biography

Giusy Iaria is a Ph.D. student in her third year in Computer and Control Engineering at Polytechnic of Turin, Italy. She is part of the CAD & Reliability research group with a strong focus on Embedded electronics testing. She took her Master's Degree in Computer Engineering at Polytechnic of Turin in 2021. After a research fellowship on the reliability of safety-critical devices, she started her Ph.D. to find strategies and evaluation methods to reach ultra-reliability in Automotive Systems-on-Chip.

Teaching

Teachings

Bachelor of Science

Computer sciences. A.A. 2022/23, INGEGNERIA DELL'AUTOVEICOLO (AUTOMOTIVE ENGINEERING). Collaboratore del corso
Computer sciences. A.A. 2023/24, INGEGNERIA DELL'AUTOVEICOLO (AUTOMOTIVE ENGINEERING). Collaboratore del corso
Computer sciences. A.A. 2024/25, INGEGNERIA DELL'AUTOVEICOLO (AUTOMOTIVE ENGINEERING). Collaboratore del corso

MostraNascondi A.A. passati

Research

Research groups

CAD - Electronic CAD & Reliability Group

Publications

Works published during the Ph.D. View all publications in Porto@Iris

Iaria, Giusy; Bernardi, Paolo; Bertani, Claudia; Cardone, Lorenzo; Garozzo, Giuseppe; ... (2025)
A Comprehensive Scan Test Cost Model to Optimize the Production of very large SoCs. In: IEEE TRANSACTIONS ON COMPUTERS, vol. 74, pp. 1278-1292. ISSN 0018-9340
Contributo su Rivista
Iaria, Giusy (2025)
Towards Ultra-Reliable Automotive Systems-on-Chip. relatore: BERNARDI, PAOLO; , 37. XXXVII Ciclo, P.: 125
Doctoral Thesis
Bernardi, Paolo; Filipponi, Gabriele; Iaria, Giusy; Bertani, Claudia; Tancorre, Vincenzo (2024)
Logic Diagnosis Based on Logic Built-In Self-Test Signatures Collected In-Field from Failing System-on-Chips. In: ELECTRONICS, vol. 13. ISSN 2079-9292
Contributo su Rivista
Bernardi, Paolo; Cardone, Lorenzo; Iaria, Giusy; Appello, Davide; Garozzo, Giuseppe; ... (2023)
About the correlation between logical identified faulty gates and their layout characteristics. In: IEEE International Symposium on On-Line Testing and Robust System Design, 03-05 July 2023, Crete, Greece. ISBN: 979-8-3503-4135-5
Contributo in Atti di Convegno (Proceeding)
Angione, F.; Appello, D.; Aribido, J.; Athavale, J.; Bellarmino, N.; Bernardi, P.; ... (2022)
Test, Reliability and Functional Safety Trends for Automotive System-on-Chip. In: 2022 IEEE European Test Symposium (ETS), Barcelona (Spain), 23-27 May 2022, pp. 1-10. ISBN: 978-1-6654-6706-3
Contributo in Atti di Convegno (Proceeding)