• INGEGNERIA INFORMATICA E DEI SISTEMI, 2024/2025 (41. ciclo)
  Politecnico di TORINO
• INGEGNERIA INFORMATICA E DEI SISTEMI, 2023/2024 (40. ciclo)
  Politecnico di TORINO
• INGEGNERIA INFORMATICA E DEI SISTEMI, 2022/2023 (39. ciclo)
  Politecnico di TORINO

• Collegio di Ingegneria Elettronica, delle Telecomunicazioni e Fisica. Componente
• Collegio di Ingegneria Informatica, del Cinema e Meccatronica. Componente

Projects funded by competitive calls

• Reinforcing Skills in Chips Design for Europe, (2024-2028) - Componente gruppo di Ricerca
  University cooperation

• CAD - Electronic CAD & Reliability Group

Projects funded by competitive calls

• REACT - Self-AwaRe NEuromorphic ArChiTectures: Security, Reliability and Energy-Efficiency , (2025-2029) - Responsabile Scientifico
  UE-funded research - HE - Excellent Science - MSCA

Projects funded by commercial contracts

• Supporto allo sviluppo e prototipazione di Interfaccia di Comunicazioni per moduli Laser ALITE , (2026-2028) - Responsabile Scientifico
  Commercial contracts for the provision of services
• Activities for supporting the development of the new Electrical/Electronic Architecture , (2025-2026) - Responsabile Scientifico
  Commercial Research
• New Electrical/Electronic Architecture Pre-study , (2024-2025) - Responsabile Scientifico
  Commercial Research
• Robotics Functional Safety , (2022-2023) - Responsabile contrattuale
  Commercial Research
• Analysis and optimization of Core SelfTest (CST) Libraries running in multi core Automotive Microcontrollers , (2021-2022) - Responsabile Scientifico
  Commercial Research
• Robotics Functional Safety , (2021-2022) - Responsabile Scientifico
  Commercial Research
• Core Self Test (CST) generation able to run in Automotive Microcontrollers multi core devices used for automotive applications , (2020-2020) - Responsabile Scientifico
  Commercial Research
• Core Self Test (CST) generation able to run in Automotive Microcontrollers multi core devices used for automotive applications , (2019-2019) - Responsabile Scientifico
  Commercial Research
• CST generation for a new 40nm Automotive Microcontroller used for automotive applications , (2018-2018) - Responsabile Scientifico
  Commercial Research
• CST generation for a 40nm Automotive Microcontroller , (2017-2017) - Responsabile Scientifico
  Commercial Research

• Lorenzo Fezza. Programme in Ingegneria Informatica E Dei Sistemi (cycle 41, 2026-in progress)
• Giacomo Perlo. Programme in Ingegneria Informatica E Dei Sistemi (cycle 41, 2025-in progress)
• Behnam Farnaghinejad. Programme in Intelligenza Artificiale (cycle 40, 2024-in progress)
  Research subject: Improving the security of embedded systems running AI applications
  
  Embedded AI
  TinyML
  Embedded AI
  TinyML
  Embedded AI
  TinyML
• Antonio Porsia. Programme in Ingegneria Informatica E Dei Sistemi (cycle 39, 2023-in progress)
  
  Computer architectures and Computer aided design
  Computer architectures and Computer aided design
• Juan David Guerrero Balaguera. Programme in Ingegneria Informatica E Dei Sistemi (cycle 36, 2020-2024)
  Thesis: Reliability Enhancement in GPU Architectures
  
  Cybersecurity
  Life sciences
  Cybersecurity
  Life sciences
• Franco Oberti. Programme in Ingegneria Informatica E Dei Sistemi (cycle 36, 2020-2024)
  Thesis: Cybersecurity for future interconnected and smart vehicles

• SANCHEZ SANCHEZ, EDGAR ERNESTO; Schillaci, Massimiliano; Squillero, Giovanni (2006)
  Enhanced Test Program Compaction Using Genetic Programming. In: CEC 2006, IEEE Congress on Evolutionary Computation, Vancouver (BC), Canada, July 16-21, 2006, pp. 865-870
  Contributo in Atti di Convegno (Proceeding)
• Bernardi, Paolo; SANCHEZ SANCHEZ, EDGAR ERNESTO; Schillaci, Massimiliano; Squillero, ... (2006)
  An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs. In: IEEE DATE 2006: Design, Automation and Test in Europe, 6-10 March 2006, pp. 412-417. ISBN: 9783981080100
  Contributo in Atti di Convegno (Proceeding)
• SANCHEZ SANCHEZ, EDGAR ERNESTO; Schillaci, Massimiliano (2006)
  A survey of µGP. In: ?Congresso?, pp. 17-21
  Contributo in Atti di Convegno (Proceeding)
• SANCHEZ SANCHEZ, EDGAR ERNESTO; Schillaci, Massimiliano; Squillero, Giovanni (2006)
  Anatomy of an extensible evolutionary tool. In: GSICE06: Giornata di Studio Italiana sul Calcolo Evolutivo, Siena, September 15 2006
  Contributo in Atti di Convegno (Proceeding)
• SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA REORDA, Matteo; Squillero, Giovanni (2006)
  Efficient Techniques for Automatic Verification-Oriented Test Set Optimization. In: INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, vol. 34, pp. 93-109. ISSN 0885-7458
  Contributo su Rivista
• Squillero, Giovanni; Schillaci, Massimiliano; SANCHEZ SANCHEZ, EDGAR ERNESTO (2006)
  µGP an evolutionary test program generator. In: IOST3, IEEE International Workshop on Open Source Test Technology Tools, Berkeley (CA), USA, April 30 2006
  Contributo in Atti di Convegno (Proceeding)
• Bernardi, Paolo; SANCHEZ SANCHEZ, EDGAR ERNESTO; Schillaci, Massimiliano; SONZA REORDA, ... (2006)
  An Evolutionary Methodology to Enhance Processor Software-Based Diagnosis. In: CEC 2006, IEEE Congress on Evolutionary Computation, Vancouver (BC), Canada, July 16-21, 2006, pp. 859-864
  Contributo in Atti di Convegno (Proceeding)
• SANCHEZ SANCHEZ, EDGAR ERNESTO; Schillaci, Massimiliano; Squillero, Giovanni (2006)
  Evolving Warriors for the Nano Core. In: CIG 2006, IEEE Symposium on Computational Intelligence and Games, Reno/Lake Tahoe (AZ), USA, May 22-24 2006, pp. 272-278
  Contributo in Atti di Convegno (Proceeding)
• SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA REORDA, Matteo; Squillero, Giovanni; Violante, ... (2005)
  Automatic Generation of Test Sets for SBST of Microprocessor IP Cores. In: 18th Symposium on Integrated Circuits and Systems Design, SBCCI, pp. 74-79. ISBN: 9781595931740
  Contributo in Atti di Convegno (Proceeding)
• SANCHEZ SANCHEZ, EDGAR ERNESTO; Schillaci, Massimiliano; SONZA REORDA, Matteo; ... (2005)
  New Evolutionary Techniques for Test-Program Generation for Complex Microprocessor Cores. In: Genetic and Evolutionary Computation Conference, pp. 2193-2194
  Contributo in Atti di Convegno (Proceeding)
• SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA REORDA, Matteo; Squillero, Giovanni (2005)
  On the transformation of manufacturing test sets into on-line test sets for microprocessors. In: Defect and Fault Tolerance in VLSI Systems (DFT), pp. 494-502. ISBN: 9780769524641
  Contributo in Atti di Convegno (Proceeding)
• SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA REORDA, Matteo; Squillero, Giovanni (2005)
  Automatic completion and refinement of verification sets for microprocessor cores. In: EvoWorkshops 2005: Applications of Evolutionary Computing, pp. 205-214. ISSN 0302-9743. ISBN: 978-3-540-25396-9
  Contributo in Atti di Convegno (Proceeding)
• SANCHEZ SANCHEZ, EDGAR ERNESTO; Squillero, Giovanni; SONZA REORDA, Matteo (2005)
  Automatic Completion and Refinement of Verification Sets for Microprocessor Cores. In: EvoWorkkshops 2005: EvoBIO, EvoCOMNET, EvoHOT, EvoIASP, EvoMUSART, and EvoSTOC, Lausanne (CHE), March 30 - April 1, 2005, pp. 205-214. ISSN 0302-9743. ISBN: 9783540253969
  Contributo in Atti di Convegno (Proceeding)
• Corno, Fulvio; SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA REORDA, Matteo; Squillero, Giovanni (2005)
  Automatic Test Generation for Verifying Microprocessors. In: IEEE POTENTIALS, vol. 24, pp. 34-37. ISSN 0278-6648
  Contributo su Rivista
• Bernardi, Paolo; Grosso, Michelangelo; Manzone, A; Rebaudengo, Maurizio; SANCHEZ ... (2005)
  Integrating BIST techniques for on-line SoC testing. In: IEEE International On-Line Test Symposium IOLTS, Saint Raphael, France, 6-8 Luglio, 2005, pp. 235-240
  Contributo in Atti di Convegno (Proceeding)
• SANCHEZ SANCHEZ, EDGAR ERNESTO; Schillaci, Massimiliano; Squillero, Giovanni (2005)
  A modular Architecture for a Populationless Evolutionary Algorithm for MIP. In: GSICE05: Giornata di Studio Italiana sul Calcolo Evolutivo, Milano, September 20 2005
  Contributo in Atti di Convegno (Proceeding)
• SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA REORDA, Matteo; Squillero, Giovanni (2005)
  Test Program Generation from High-level Microprocessor Descriptions. In: System-level Test and Validation of Hardware/Software Systems / AA.VV., BERLIN, Springer, pp. 83-106. ISBN: 9781852338992
  Contributo in Volume
• Bernardi, Paolo; SANCHEZ SANCHEZ, EDGAR ERNESTO; Schillaci, Massimiliano; SONZA REORDA, ... (2005)
  Diagnosing faulty functional units in processors by using automatically generated test sets. In: Sixth International Workshop on Microprocessor Test and Verification, 2005. MTV '05, Austin, TX (USA), 3-5 Nov. 2005. ISBN: 0769526276
  Contributo in Atti di Convegno (Proceeding)
• Corno, Fulvio; SANCHEZ SANCHEZ, EDGAR ERNESTO; Squillero, Giovanni (2005)
  Evolving assembly programs: how games help microprocessor validation. In: IEEE TRANSACTIONS ON EVOLUTIONARY COMPUTATION, vol. 9, pp. 695-706. ISSN 1089-778X
  Contributo su Rivista
• L., Anghel; SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA REORDA, Matteo; Squillero, Giovanni; ... (2004)
  Coupling different methodologies to validate obsolete microprocessors. In: Defect and Fault Tolerance in VLSI Systems, pp. 250-255. ISBN: 9780769522418
  Contributo in Atti di Convegno (Proceeding)

• A Shannon-Hartley-Based Approach To Measure The Criticality Of Synaptic Weights. international Patent
  Inventors: Annachiara Ruospo Edgar Ernesto Sanchez Sanchez