Ph.D. in Ingegneria Elettrica, Elettronica E Delle Comunicazioni , 37th cycle (2021-2024)
Ph.D. obtained in 2025
Dissertation:
Making acceleration more amenable with novel high-level synthesis techniques for FPGAs (Abstract)
Tutors:
Luciano LavagnoProfile
Research topic
Improving Quality of Results for HLS designs
Research interests
Teaching
Teachings
Master of Science
- Modeling and optimization of embedded systems. A.A. 2024/25, INGEGNERIA INFORMATICA (COMPUTER ENGINEERING). Collaboratore del corso
Publications
Works published during the Ph.D. View all publications in Porto@Iris
- Brignone, Giovanni (2025)
Making acceleration more amenable with novel high-level synthesis techniques for FPGAs. relatore: LAVAGNO, Luciano; , 37. XXXVII Ciclo, P.: 64
Doctoral Thesis - Brignone, Giovanni; Bosio, Roberto; Ottati, Fabrizio; Sansoe', Claudio; Lavagno, Luciano (2025)
SILVIA: Automated Superword-Level Parallelism Exploitation via HLS-Specific LLVM Passes for Compute-Intensive FPGA Accelerators. In: ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS, vol. 18. ISSN 1936-7406
Contributo su Rivista - Bosio, Roberto; Brignone, Giovanni; Urso, Teodoro; Lazarescu, Mihai T.; Lavagno, ... (2025)
Low-Power Subgraph Isomorphism at the Edge Using FPGAs. In: IEEE ACCESS, vol. 13, pp. 67127-67135. ISSN 2169-3536
Contributo su Rivista - Bosio, Roberto; Brignone, Giovanni; Minnella, Filippo; Jamal, MUHAMMAD USMAN; Lavagno, ... (2024)
LESS: Low-Power Energy-Efficient Subgraph Isomorphism on FPGA. In: 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), Valencia (Spain), 25-27 March 2024, pp. 1-2. ISBN: 978-3-9819263-8-5
Contributo in Atti di Convegno (Proceeding) - Ottati, Fabrizio; Gao, Chang; Chen, Qinyu; Brignone, Giovanni; Casu, Mario Roberto; ... (2023)
To Spike or Not To Spike: A Digital Hardware Perspective on Deep Learning Acceleration. In: IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, vol. 13, pp. 1015-1025. ISSN 2156-3365
Contributo su Rivista - Brignone, Giovanni; Lazarescu, Mihai T.; Lavagno, Luciano (2023)
A DSP shared is a DSP earned: HLS Task-Level Multi-Pumping for High-Performance Low-Resource Designs. In: 2023 IEEE 41st International Conference on Computer Design (ICCD), Washington (USA), 06-08 November 2023, pp. 551-557. ISBN: 979-8-3503-4291-8
Contributo in Atti di Convegno (Proceeding) - Brignone, Giovanni; Jamal, Muhammad Usman; Lazarescu, Mihai T.; Lavagno, Luciano (2022)
Array-specific dataflow caches for high-level synthesis of memory-intensive algorithms on FPGAs. In: IEEE ACCESS, vol. 10, pp. 118858-118877. ISSN 2169-3536
Contributo su Rivista