
Ph.D. in Ingegneria Elettrica, Elettronica E Delle Comunicazioni , 35th cycle (2019-2022)
Ph.D. obtained in 2023
Dissertation:
Techniques and Optimization Strategies for Efficient Hardware Acceleration of Neural Networks: Tap-Wisely-Quantized Winograd Algorithm and Capsule Networks (Abstract)
Tutors:
Maurizio Martina
Research presentation:
Video presentationProfile
Research topic
Hardware accelerators for Deep Neural Networks training and inference
Research interests
Biography
Teaching
Teachings
Master of Science
- Integrated systems architecture. A.A. 2020/21, INGEGNERIA ELETTRONICA (ELECTRONIC ENGINEERING). Collaboratore del corso
Bachelor of Science
- Elettronica applicata. A.A. 2020/21, INGEGNERIA ELETTRONICA. Collaboratore del corso
- Elettronica applicata. A.A. 2021/22, INGEGNERIA ELETTRONICA. Collaboratore del corso
Publications
Works published during the Ph.D. View all publications in Porto@Iris
- Bussolino, Beatrice (2023)
Techniques and Optimization Strategies for Efficient Hardware Acceleration of Neural Networks: Tap-Wisely-Quantized Winograd Algorithm and Capsule Networks. relatore: MARTINA, MAURIZIO; , 35. XXXV Ciclo, P.: 167
Doctoral Thesis - Marchisio, Alberto; Mrazek, Vojtech; Massa, Andrea; Bussolino, Beatrice; Martina, ... (2022)
RoHNAS: A Neural Architecture Search Framework with Conjoint Optimization for Adversarial Robustness and Hardware Efficiency of Convolutional and Capsule Networks. In: IEEE ACCESS, vol. 10, pp. 109043-109055. ISSN 2169-3536
Contributo su Rivista - Marchisio, Alberto; Bussolino, Beatrice; Salvati, Edoardo; Martina, Maurizio; Masera, ... (2022)
Enabling Capsule Networks at the Edge through Approximate Softmax and Squash Operations. In: ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston (USA), 1-2 August 2022. ISBN: 9781450393546
Contributo in Atti di Convegno (Proceeding) - Aiello, Giuseppe; Bussolino, Beatrice; Valpreda, Emanuele; Ruo Roch, Massimo; Masera, ... (2022)
NLCMAP: A Framework for the Efficient Mapping of Non-Linear Convolutional Neural Networks on FPGA Accelerators. In: International Conference on Image Processing, Bordeaux, France, 16-19 October 2022. ISBN: 978-1-6654-9620-9
Contributo in Atti di Convegno (Proceeding) - Marchisio, Alberto; Bussolino, Beatrice; Colucci, Alessio; Hanif, Muhammad Abdullah; ... (2020)
FasTrCaps: An Integrated Framework for Fast yet Accurate Training of Capsule Networks. In: 2020 International Joint Conference on Neural Networks (IJCNN), Glasgow (UK), 19-24 July 2020, pp. 1-8. ISBN: 978-1-7281-6926-2
Contributo in Atti di Convegno (Proceeding) - Capra, Maurizio; Bussolino, Beatrice; Marchisio, Alberto; Shafique, Muhammad; Masera, ... (2020)
An Updated Survey of Efficient Hardware Architectures for Accelerating Deep Convolutional Neural Networks. In: FUTURE INTERNET, vol. 12, pp. 113-134. ISSN 1999-5903
Contributo su Rivista - Capra, M.; Bussolino, B.; Marchisio, A.; Masera, G.; Martina, M.; Shafique, M. (2020)
Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead. In: IEEE ACCESS, vol. 8, pp. 225134-225180. ISSN 2169-3536
Contributo su Rivista - Marchisio, Alberto; Massa, Andrea; Mrazek, Vojtech; Bussolino, Beatrice; Martina, ... (2020)
NASCaps: A Framework for Neural Architecture Search to Optimize the Accuracy and Hardware Efficiency of Convolutional Capsule Networks. In: 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD), Virtual Event, USA, 2 - 5 Novembre, pp. 1-9. ISBN: 9781450380263
Contributo in Atti di Convegno (Proceeding) - Marchisio, Alberto; Bussolino, Beatrice; Colucci, Alessio; Martina, Maurizio; Masera, ... (2020)
Q-CapsNets: A Specialized Framework for Quantizing Capsule Networks. In: 2020 57th ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, USA, 20-24 July 2020, pp. 1-6. ISBN: 978-1-7281-1085-1
Contributo in Atti di Convegno (Proceeding) - Colucci, Alessio; Marchisio, Alberto; Bussolino, Beatrice; Mrazek, Voitech; Martina, ... (2020)
A Fast Design Space Exploration Framework for the Deep Learning Accelerators: Work-in-Progress. In: International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Singapore, 20-25 September 2020, pp. 34-36. ISBN: 978-1-7281-9198-0
Contributo in Atti di Convegno (Proceeding)