Corso di laurea di 1° livello

• Computer sciences. A.A. 2013/14, INGEGNERIA DELL'AUTOVEICOLO (AUTOMOTIVE ENGINEERING). Collaboratore del corso
• Computer sciences. A.A. 2013/14, INGEGNERIA DELL'AUTOVEICOLO (AUTOMOTIVE ENGINEERING). Collaboratore del corso
• Computer sciences. A.A. 2012/13, INGEGNERIA DELL'AUTOVEICOLO (AUTOMOTIVE ENGINEERING). Collaboratore del corso
• Computer sciences. A.A. 2012/13, INGEGNERIA DELL'AUTOVEICOLO (AUTOMOTIVE ENGINEERING). Collaboratore del corso

• Sterpone, Luca; Ullah, Anees (In stampa)
  Real-Time SEU Tolerant Circuits on SRAM-based FPGAs. In: Radiation Effects on Components and Systems 2013, Oxford, 23rd-27th September, 2013
  Contributo in Atti di Convegno (Proceeding)
• Desogus, Marco; Sterpone, Luca; Sabena, Davide; Ullah, Anees; Mario, Porrmann; Jens, ... (In stampa)
  Hardening Dynamically Reconfigurable Processing Modules Architectures: A Neutron Test Experience. In: Radiation Effects on Components and Systems 2013
  Contributo in Atti di Convegno (Proceeding)
• Ullah, A.; Sanchez, E.; Sterpone, L.; Cardona, L. A.; Ferrer, C. (2017)
  An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs. In: MICROELECTRONICS RELIABILITY, vol. 75, pp. 110-120. ISSN 0026-2714
  Contributo su Rivista
• SONZA REORDA, Matteo; Sterpone, Luca; Ullah, Anees (2017)
  An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable Systems. In: IEEE TRANSACTIONS ON COMPUTERS, vol. 66, pp. 1022-1033. ISSN 0018-9340
  Contributo su Rivista
• Ullah, Anees (2015)
  Dependable System Design for Reconfigurable Safety-Critical Applications. relatore: STERPONE LUCA, 27. XXVII Ciclo, P.: 111
  Doctoral Thesis
• Ullah, Anees; Sterpone, Luca (2014)
  Recovery Time and Fault Tolerance Improvement for Circuits mapped on SRAM-based FPGAs. In: JOURNAL OF ELECTRONIC TESTING, vol. 30, pp. 425-442. ISSN 0923-8174
  Contributo su Rivista
• SANCHEZ SANCHEZ, EDGAR ERNESTO; Sterpone, Luca; Ullah, Anees (2014)
  Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs. In: 24th International Conference on Field Programmable Logic and Applications (FPL), 2014, pp. 1-6
  Contributo in Atti di Convegno (Proceeding)
• Sterpone, Luca; Sabena, Davide; Ullah, Anees; Porrmann, M.; Hagemeyer, J.; Ilstad, J. (2013)
  Dynamic Neutron Testing of Dynamically Reconfigurable Processing Modules Architecture. In: IEEE AHS, Torino, June 2013, pp. 184-188
  Contributo in Atti di Convegno (Proceeding)
• Sterpone, Luca; Ullah, Anees (2013)
  On the Optimal Reconfiguration Times for TMR Circuits on SRAM based FPGAs. In: IEEE AHS, Torino, June 2013, pp. 9-14
  Contributo in Atti di Convegno (Proceeding)
• SONZA REORDA, Matteo; Sterpone, Luca; Ullah, Anees (2013)
  An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable Systems. In: IEEE European Test Symposium, pp. 149-155
  Contributo in Atti di Convegno (Proceeding)
• Ullah, Anees; Hazrat, Ali; Yasir Ali, Khan; Muhammad, Aamir; Nazim, Ali; K. M., Yahya (2012)
  Phase compensated differential based quadrature direct digital frequency synthesis. In: 2012 International Conference on Emerging Technologies (ICET), pp. 1-6. ISBN: 9781467344524
  Contributo in Atti di Convegno (Proceeding)