Dottorato in Ingegneria Informatica E Dei Sistemi , 20o ciclo (2005-2007)
Dottorato concluso nel 2008
Tesi:
New Techniques for Highly Reliable Systems-on-Chip
Tutori:
Matteo Sonza ReordaPubblicazioni
Pubblicazioni durante il dottorato Vedi tutte le pubblicazioni su Porto@Iris
- VEIRAS BOLZANI, Leticia Maria; Sanchez, E.; SONZA REORDA, Matteo (2007)
On Test Program Generation for Peripheral Components in a SoC Resorting to High-Level Metrics. In: 8th IEEE Latin American Test Workshop - LATW'07, Lima, Peru, March 11-14
Contributo in Atti di Convegno (Proceeding) - Bernardi, Paolo; VEIRAS BOLZANI, Leticia Maria; SONZA REORDA, Matteo (2007)
Extended Fault Detection Techniques for Systems-on-Chip. In: DDECS2007: IEEE Design & Diagnostic of Electronic Circuits & Systems, Krakow, Poland, April 2007, pp. 55-60
Contributo in Atti di Convegno (Proceeding) - Bernardi, Paolo; VEIRAS BOLZANI, Leticia Maria; SONZA REORDA, Matteo (2007)
A Hybrid Approach to Fault Detection and Correction in SoCs. In: IOLTS2007: IEEE International On-Line Testing Symposium, Hersonissos, Greece, July 2007, pp. 107-112
Contributo in Atti di Convegno (Proceeding) - VEIRAS BOLZANI, Leticia Maria; Bernardi, Paolo; SONZA REORDA, Matteo (2007)
An optimized hybrid approach to provide fault detection and correction in SoCs. In: SBCCI2007: IEEE 20th SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, Rio de Janeiro, September 2007, pp. 342-347
Contributo in Atti di Convegno (Proceeding) - VEIRAS BOLZANI, Leticia Maria; SANCHEZ SANCHEZ, EDGAR ERNESTO; Schillaci, Massimiliano; ... (2007)
An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores. In: IOLTS2007: IEEE International On-Line Testing Symposium, Hersonissos-Heraklion, Crete, Greece, 8-11 July 2007, pp. 265-270. ISBN: 9780769529189
Contributo in Atti di Convegno (Proceeding) - VEIRAS BOLZANI, Leticia Maria; SANCHEZ SANCHEZ, EDGAR ERNESTO; Schillaci, Massimiliano; ... (2007)
Coupling EA and High-Level Metrics for the Automatic Generation of Test Blocks for Peripheral Cores. In: GECCO, London, July 2007, pp. 1912-1919
Contributo in Atti di Convegno (Proceeding) - VEIRAS BOLZANI, Leticia Maria; SANCHEZ SANCHEZ, EDGAR ERNESTO; Schillaci, Massimiliano; ... (2007)
Co-evolution of Test Programs and Stimuli Vectors for Testing of Embedded Peripheral Cores. In: CEC 2007, IEEE Congress on Evolutionary Computation, pp. 3474-3481
Contributo in Atti di Convegno (Proceeding) - VEIRAS BOLZANI, Leticia Maria; SANCHEZ SANCHEZ, EDGAR ERNESTO; SONZA REORDA, Matteo (2007)
A Software-based Methodology for the Generation of Peripheral Test Sets Based on High-level Descriptions. In: SBCCI2007: ACM 20th SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, pp. 348-353. ISBN: 9781595938169
Contributo in Atti di Convegno (Proceeding) - Bernardi, Paolo; VEIRAS BOLZANI, Leticia Maria; Violante, Massimo; SONZA REORDA, Matteo; ... (2006)
Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications. In: ?Congresso?
Contributo in Atti di Convegno (Proceeding) - Bernardi, Paolo; VEIRAS BOLZANI, Leticia Maria; Rebaudengo, Maurizio; SONZA REORDA, ... (2006)
A new hybrid fault detection technique for systems-on-a-chip. In: IEEE TRANSACTIONS ON COMPUTERS, vol. 55, pp. 185-198. ISSN 0018-9340
Contributo su Rivista - Bernardi, Paolo; VEIRAS BOLZANI, Leticia Maria; Rebaudengo, Maurizio; SONZA REORDA, ... (2005)
Pandora I-IP: an HW/SW approach to Control Flow Checking. In: 6th IEEE Latin American Test Workshop - LATW'05, Bahia Brazil, March 30 - April 2
Contributo in Atti di Convegno (Proceeding) - Bernardi, Paolo; VEIRAS BOLZANI, Leticia Maria; Rebaudengo, Maurizio; SONZA REORDA, ... (2005)
An integrated approach for increasing the soft-error detection capabilities in SoCs processors. In: IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 307-312
Contributo in Atti di Convegno (Proceeding) - Bernardi, Paolo; VEIRAS BOLZANI, Leticia Maria; Rebaudengo, Maurizio; SONZA REORDA, ... (2005)
On-line Detection of Control-Flow Errors in SoCs by means of an Infrastructure IP core. In: IEEE Dependable Systems and Networks Symposium, pp. 50-58
Contributo in Atti di Convegno (Proceeding)