Dottorato in Ingegneria Informatica E Dei Sistemi , 21o ciclo (2006-2008)
Dottorato concluso nel 2009
Tesi:
Variation Aware Design Methodologies for Nanometer CMOS Designs.
Tutori:
Enrico MaciiPubblicazioni
Pubblicazioni più recenti Vedi tutte le pubblicazioni su Porto@Iris
- Calimera, Andrea; Duraisami, Karthik; VISWESWARA SATHANUR, Ashoka; Sithambaram, P; ... (2008)
Thermal-Aware Design Techniques for Nanometer CMOS Circuits. In: JOURNAL OF LOW POWER ELECTRONICS, vol. 3, pp. 374-384. ISSN 1546-1998
Contributo su Rivista - Chakraborty, A.; Duraisami, Karthik; VISWESWARA SATHANUR, Ashoka; Sithambaram, P.; ... (2008)
Dynamic thermal clock skew compensation using tunable delay buffers. In: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, vol. 16, pp. 639-649. ISSN 1063-8210
Contributo su Rivista - Duraisami, Karthik; Poncino, Massimo; Macii, Enrico (2008)
Energy Efficiency Bounds of Pulse-Encoded Buses. In: GLS-VLSI-08: ACM/IEEE 18th Great Lakes Symposium on VLSI, Orlando, FL, pp. 183-188. ISBN: 9781595939999
Contributo in Atti di Convegno (Proceeding) - Duraisami, Karthik; Sithambaram, P; Sathanur, A; Macii, Alberto; Macii, Enrico; Poncino, ... (2007)
Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew. In: ISCAS-07: IEEE International Conference on Circuits and Systems, New Orleans, Louisiana, 27-30 May 2007, pp. 1061-1064. ISBN: 1424409209
Contributo in Atti di Convegno (Proceeding) - Ashutosh, Chakraborty; Duraisami, Karthik; VISWESWARA SATHANUR, A.; Prassanna, ... (2006)
Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective. In: PATMOS-06: IEEE International Workshop on Power and Timing Modeling, Optimization and Simulation, Montpellier, France, pp. 214-224. ISBN: 3540390944
Contributo in Atti di Convegno (Proceeding)