Luca Sterpone

Foto di Luca Sterpone

Dottorato in Ingegneria Informatica E Dei Sistemi , 19o ciclo (2004-2006)

Dottorato concluso nel 2007

Tesi:

Electronic System Design Techniques for safety Critical Applications.

Tutori:

Matteo Sonza Reorda

Profilo

Interessi di ricerca

Embedded system design

Settore scientifico discliplinare

IINF-05/A - Sistemi di elaborazione delle informazioni
(Area 0009 - Ingegneria industriale e dell'informazione)

Premi e riconoscimenti

Didattica

Collegi di Dottorato

  • INGEGNERIA INFORMATICA E DEI SISTEMI, 2023/2024 (40. ciclo)
    Politecnico di TORINO
  • INGEGNERIA INFORMATICA E DEI SISTEMI, 2022/2023 (39. ciclo)
    Politecnico di TORINO
  • INGEGNERIA INFORMATICA E DEI SISTEMI, 2021/2022 (38. ciclo)
    Politecnico di TORINO
  • INGEGNERIA INFORMATICA E DEI SISTEMI, 2020/2021 (37. ciclo)
    Politecnico di TORINO
  • INGEGNERIA INFORMATICA E DEI SISTEMI, 2019/2020 (36. ciclo)
    Politecnico di TORINO
  • INGEGNERIA INFORMATICA E DEI SISTEMI, 2018/2019 (35. ciclo)
    Politecnico di TORINO
  • INGEGNERIA INFORMATICA E DEI SISTEMI, 2017/2018 (34. ciclo)
    Politecnico di TORINO
  • INGEGNERIA INFORMATICA E DEI SISTEMI, 2016/2017 (33. ciclo)
    Politecnico di TORINO
  • INGEGNERIA INFORMATICA E DEI SISTEMI, 2015/2016 (32. ciclo)
    Politecnico di TORINO
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Collegi dei Corsi di Studio

Progetti di didattica e formazione finanziati da enti esterni

Progetti finanziati da bandi competitivi

Progetti finanziati da contratti commerciali

Altre attività e progetti di didattica

The teaching activity of Luca Sterpone has been focused on three fundamental courses for the Bachelor degree (Laurea) in Computer Engineering: Computer Science, Computer Architecture and Operating Systems.

Luca Sterpone actively contributes to the innovation of the courses contents in particular promoting the adoption of state-of-the-art scripting language for the courses of Operating Systems and contributing to the adoption of modern MIPS architecture for the course of Computer Architecture. Besides, since the academic year 2014/2015, Luca Sterpone is formal responsible of the PhD course of Reconfigurable Computing whose content has been personally created and managed. The course is constantly updated with the research advancements in the area of reconfigurable computing and it has an average of 15 PhD students per academic year.

• Formal responsibility of Bachelor’s (Laurea) and Master of Science’s (Laurea Magistrale) degree courses in Italian and/or foreign universities

- Computer Science, Politecnico di Torino, Italian language, 9 years, (A.A. 2010/2011, 2011/2012, 2012/2013, 2013/2014, 2014/2015, 2015/2016, 2016/2017, 2017/2018, 2018/2019)
- Operating Systems, Politecnico di Torino, Italian language, 7 years (A.A. 2014/2015, 2015/2016, 2016/2017, 2017/2018, 2018/2019, 2019/2020, 2020/2021)
- Computer Architecture, Politecnico di Torino, Italian language, 3 years (A.A. 2018/2019, 2019/2020, 2020/2021)

• Formal responsibility of PhD courses in Italian and/or foreign universities.

- Reconfigurable Computing, English, 7 years (A.A. 2014/2015, 2015/2016, 2016/2017, 2017/2018, 2018/2019, 2019/2020, 2020/2021)

Ricerca

Gruppi di ricerca

Progetti di ricerca

Progetti finanziati da bandi competitivi

Progetti finanziati da contratti commerciali

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Dottorandi

  • Arash Amini Bardpareh. Corso in Ingegneria Informatica E Dei Sistemi (ciclo 40, 2025-in corso)
  • Federico Buccellato. Corso in Ingegneria Informatica E Dei Sistemi (ciclo 40, 2024-in corso)
    Computer architectures and Computer aided design
    Data science, Computer vision and AI
    Parallel and distributed systems, Quantum computing
    Software engineering and Mobile computing
    Computer architectures and Computer aided design
    Data science, Computer vision and AI
    Parallel and distributed systems, Quantum computing
    Software engineering and Mobile computing
  • Aobo Cui. Corso in Ingegneria Informatica E Dei Sistemi (ciclo 40, 2025-in corso)
  • Giorgio Cora. Corso in Ingegneria Informatica E Dei Sistemi (ciclo 39, 2023-in corso)
    Computer architectures and Computer aided design
    Computer architectures and Computer aided design
  • Rosario Milazzo. Corso in Ingegneria Informatica E Dei Sistemi (ciclo 38, 2023-in corso)
    Argomento della ricerca: Robust, accurate and efficient deep neural networks for satellite and mobility applications
    Data science, Computer vision and AI
    Data science, Computer vision and AI
    Data science, Computer vision and AI
  • Andrea Portaluri. Corso in Ingegneria Informatica E Dei Sistemi (ciclo 37, 2021-in corso)
  • Eleonora Vacca. Corso in Ingegneria Informatica E Dei Sistemi (ciclo 37, 2021-in corso)
    Argomento della ricerca: Metodi di progettazione di acceleratori riconfigurabili per applicazioni spaziali ad alta affidabilità
    Computer architectures and Computer aided design
  • Corrado De Sio. Corso in Ingegneria Informatica E Dei Sistemi (ciclo 35, 2019-2023)
    Tesi: Toward Fault-Tolerant Applications on Reconfigurable Systems-on-Chip
    Controls and system engineering
    Cybersecurity
    Controls and system engineering
    Cybersecurity
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Altre attività e progetti di ricerca

Luca Sterpone coordinates the “Aerospace and Reconfigurable Computing Team” within the Dipartimento di Automatica e Informatica of Politecnico di Torino. The group is federated within the CAD group leaded by Prof. Matteo Sonza Reorda. All the people of the “Aerospace and Reconfigurabble Computing Team” are fully managed by Luca Sterpone in terms of financial support (contracts, missions and other expenses), research support (computers, boards and any type of equipment). The group includes the following member:

- Boyang Du, Assistant Professor – RTD-A
- Sarah Azimi, Post-Doc
- Ludovica Bozzoli, PhD Student, Cycle 33
- Corrado De Sio, PhD Student, Cycle 35

Luca Sterpone coordinates different collaborations at the national and international level:
- Coordination of the research activity with the Computing System for Space (COSYSPACE) leaded by Monica Alderighi of the Istituto Nazionale di Astrofisica (INAF).
- Principal Investigator of the Politecnico di Torino group within the VEGAS H2020 project.
- Coordination of the research activity with the group Radiation Effects and Circuit Designs (RADUS) ofl Prof. Miguel Angel Aguirre Echànove from School of Engineering of Sevilla.
- Management with the Xilinx INC company of the “Single Event Effects European Consortium” supported by Xilinx INC,
- General Motor (GM). In the framework of the research collaboration, Luca Sterpone coordinates the research activity with the Electronics, SW Integration and Testing and Control GM control group.
- European Space Agency (ESA). In the framework of the research collaboration, Luca Sterpone coordinates the research activity with the ASIC/FPGA Engineer division TEC-EDM of ESA.
- Thales Alenia Space (TAS). In the framework of the research collaboration, Luca Sterpone coordinates the research activity related to the radiation test execution, analysis tools and mitigation for ASIC and FPGA devices for space satellites.

Luca Sterpone has been the academic tutor of the Reconfigurable Unmanned Aerial Vehicle (ReCoUAV) project for the Alta Scuola Politecnica (ASP) in the period 2012 – 2014 managing eight students divided in two teams with the purpose of investigating the potential future applications of Unmanned Aerial Vehicles (UAVs) based on a reconfigurable flight computer for civil purpose [PR1].
• Scientific responsibility (Principal investigator) of Italian and International research projects, awarded through a peer-review process
- Luca Sterpone has been the scientific responsible (Principal Investigator) of the Politecnico di Torino research unit in the framework of the European Innovation Triangle Initiative (ITI) entitled “On-line Testing and Healing Permanent Radiation Effects in Reconfigurable Systems” – code A00016022 with the following other research units:
European Space Agency
University of Bielefeld
Università di Pisa
Politecnico di Torino

- Luca Sterpone is the scientific responsible of the Politecnico di Torino research unit in the framework of the H2020 VEGAS - Validation of European High Capacity rad-hard FPGA and software tools - http://vegas.nanoxplore.com/


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