Mihai Teodor Lazarescu

ERC sectors

SDG

• Effective member - IEEE - Institute of Electrical and Electronics Engineers, Stati Uniti (2019-)

• SENSORS (2018-2020), Guest Editor of magazine or editorial series
• SENSORS (2017-2019), Guest Editor of magazine or editorial series
• ELECTRONICS (2016-2018), Guest Editor of magazine or editorial series
• SENSORS (2015-2016), Guest Editor of magazine or editorial series
• SENSORS (2014), Guest Editor of magazine or editorial series
• ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS (2013-2014), Guest Editor of magazine or editorial series

• International Conference on Application of Concurrency to System Design, Program chair

• Collegio di Ingegneria Elettronica, delle Telecomunicazioni e Fisica. Componente
• Collegio di Ingegneria Informatica, del Cinema e Meccatronica. Componente

Master of Science

• Challenge@Polito by Students - IoT (CIM 4.0). A.A. 2022/23, INGEGNERIA GESTIONALE (ENGINEERING AND MANAGEMENT). Collaboratore del corso
• Modeling and optimization of embedded systems. A.A. 2021/22, INGEGNERIA INFORMATICA (COMPUTER ENGINEERING). Collaboratore del corso
• Digital Electronics. A.A. 2020/21, INGEGNERIA ELETTRONICA (ELECTRONIC ENGINEERING). Collaboratore del corso
• Modeling and optimization of embedded systems. A.A. 2020/21, INGEGNERIA INFORMATICA (COMPUTER ENGINEERING). Collaboratore del corso
• Digital Electronics. A.A. 2019/20, INGEGNERIA ELETTRONICA (ELECTRONIC ENGINEERING). Collaboratore del corso
• Modeling and optimization of embedded systems. A.A. 2019/20, INGEGNERIA INFORMATICA (COMPUTER ENGINEERING). Collaboratore del corso

Bachelor of Science

• Applied electronics. A.A. 2024/25, INGEGNERIA ELETTRONICA. Titolare del corso
• Progettazione elettronica digitale. A.A. 2024/25, INGEGNERIA INFORMATICA. Titolare del corso
• Applied electronics. A.A. 2023/24, INGEGNERIA ELETTRONICA. Titolare del corso
• Elettronica applicata. A.A. 2023/24, INGEGNERIA INFORMATICA. Titolare del corso
• Applied electronics. A.A. 2022/23, INGEGNERIA ELETTRONICA. Titolare del corso
• Elettronica applicata. A.A. 2022/23, INGEGNERIA INFORMATICA. Titolare del corso
• Applied electronics. A.A. 2021/22, INGEGNERIA ELETTRONICA. Titolare del corso
• Elettronica applicata. A.A. 2021/22, INGEGNERIA INFORMATICA. Collaboratore del corso
• Elettronica applicata. A.A. 2020/21, INGEGNERIA INFORMATICA. Titolare del corso
• Applied electronics. A.A. 2020/21, INGEGNERIA INFORMATICA (COMPUTER ENGINEERING). Collaboratore del corso
• Sistemi elettronici, tecnologie e misure. A.A. 2019/20, INGEGNERIA INFORMATICA. Collaboratore del corso
• Elettronica applicata. A.A. 2019/20, INGEGNERIA INFORMATICA. Collaboratore del corso
• Applied electronics. A.A. 2019/20, INGEGNERIA INFORMATICA. Collaboratore del corso

• Hardware-accelerated machine learning for human localization, identification and behavior inference (DET)
• System-level design via high-level synthesis (DET)
• Tagless indoor person localization and identification (DET)

• Ambient sensing and processing (DET)
• High-performance software acceleration on heterogeneous CPU/GPU/FPGA platforms (DET)

Projects funded by commercial contracts

• Attività di ricerca relative al Progetto ETALON H2020-S2RJU-2017/H2020-S2RJU-OC-2017. , (2018-2018) - Responsabile Scientifico
  Commercial Research

• Roberto Bosio. Programme in Ingegneria Elettrica, Elettronica E Delle Comunicazioni (39^th cycle, 2023-in progress)
  Research subject: Acceleration of data center and embedded applications using FPGAs
  
  Big Data, Machine Learning, Neural Networks and Data Science
  Big Data, Machine Learning, Neural Networks and Data Science
• Emanuel Cascione. Programme in Ingegneria Elettrica, Elettronica E Delle Comunicazioni (39^th cycle, 2023-in progress)
• Filippo Minnella. Programme in Ingegneria Elettrica, Elettronica E Delle Comunicazioni (36^th cycle, 2020-2024)
  Thesis: Mix & Latch: High-Performance Designs with Single-Clock Mixed-Polarity Latches and Flip-Flops
  
  Big Data, Machine Learning, Neural Networks and Data Science
  Modeling, simulation and CAD
  VLSI theory, design and applications
  Big Data, Machine Learning, Neural Networks and Data Science
  Modeling, simulation and CAD
  VLSI theory, design and applications
• Giorgia Subbicini. Programme in Ingegneria Elettrica, Elettronica E Delle Comunicazioni (36^th cycle, 2020-2024)
  Thesis: Efficient Indoor Human Sensing and Continuous Tracking
  
  Analog, Power and Mixed-Signal Circuits and Embedded Systems
  Big Data, Machine Learning, Neural Networks and Data Science
  VLSI theory, design and applications
  Analog, Power and Mixed-Signal Circuits and Embedded Systems
  Big Data, Machine Learning, Neural Networks and Data Science
  VLSI theory, design and applications

• Lagostina, Lorenzo; Minnella, Filippo; Cortadella, Jordi; Casu, Mario R.; Lazarescu, ... (2024)
  Mix & Latch: Comparison With State-of-the-Art Retiming On a RISC-V Benchmark. In: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, vol. 43, pp. 2229-2233. ISSN 0278-0070
  Contributo su Rivista
• Bosio, Roberto; Minnella, Filippo; Urso, Teodoro; Casu, Mario R.; Lavagno, Luciano; ... (2024)
  NN2FPGA: Optimizing CNN Inference on FPGAs With Binary Integer Programming. In: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. ISSN 0278-0070
  Contributo su Rivista
• Subbicini, Giorgia; Lavagno, Luciano; Lazarescu, Mihai T. (2023)
  Enhanced Exploration of Neural Network Models for Indoor Human Monitoring. In: 2023 9th International Workshop on Advances in Sensors and Interfaces (IWASI), Monopoli (Bari), Italy, 08-09 June 2023, pp. 109-114. ISBN: 979-8-3503-3694-8
  Contributo in Atti di Convegno (Proceeding)
• Minnella, Filippo; Cortadella, Jordi; Casu, Mario R.; Lazarescu, Mihai T.; Lavagno, ... (2023)
  Mix & Latch: An Optimization Flow for High-Performance Designs with Single-Clock Mixed-Polarity Latches and Flip-Flops. In: IEEE ACCESS, vol. 11, pp. 1-1. ISSN 2169-3536
  Contributo su Rivista
• Brignone, Giovanni; Lazarescu, Mihai T.; Lavagno, Luciano (2023)
  A DSP shared is a DSP earned: HLS Task-Level Multi-Pumping for High-Performance Low-Resource Designs. In: 2023 IEEE 41st International Conference on Computer Design (ICCD), Washington (USA), 06-08 November 2023, pp. 551-557. ISBN: 979-8-3503-4291-8
  Contributo in Atti di Convegno (Proceeding)
• Jamal, MUHAMMAD USMAN; Li, Zhuowei; Lazarescu, MIHAI T.; Lavagno, Luciano (2023)
  A Graph Neural Network Model for Fast and Accurate Quality of Result Estimation for High-Level Synthesis. In: IEEE ACCESS, vol. 11, pp. 85785-85798. ISSN 2169-3536
  Contributo su Rivista
• Shah, NASIR ALI; Lazarescu, Mihai T.; Quasso, Roberto; Lavagno, Luciano (2023)
  CUDA-Optimized GPU Acceleration of 3GPP 3D Channel Model Simulations for 5G Network Planning. In: ELECTRONICS, vol. 15. ISSN 2079-9292
  Contributo su Rivista
• Biradar, R. C.; Geetha, D.; Tabassum, N.; Hegde, N.; Lazarescu, M. (2023)
  AI and blockchain applications in industrial robotics. Hershey, Pennsylvania, USA, IGI Global, P. 414. ISBN: 9798369306598
  Libro
• Shah, NASIR ALI; Lavagno, Luciano; Lazarescu, Mihai T.; Quasso, Roberto; Scarpina, ... (2022)
  FPGA Acceleration of 3GPP Channel Model Emulator for 5G New Radio. In: IEEE ACCESS, vol. 10, pp. 119386-119401. ISSN 2169-3536
  Contributo su Rivista
• Subbicini, Giorgia; Lavagno, Luciano; Lazarescu, Mihai T. (2022)
  Drift Rejection Differential Frontend for Single Plate Capacitive Sensors. In: IEEE SENSORS JOURNAL, vol. 22, pp. 16141-16149. ISSN 1530-437X
  Contributo su Rivista
• Shan, Junnan; Lazarescu, MIHAI TEODOR; Cortadella, Jordi; Lavagno, Luciano; Casu, MARIO ... (2022)
  Fast Energy-Optimal Multi-Kernel DNN-like Application Allocation on Multi-FPGA Platforms. In: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, vol. 41, pp. 1186-1190. ISSN 0278-0070
  Contributo su Rivista

• Noise cancellation for single-plate capacitive sensors using differential measurements. national Patent
  Inventors: Luciano Lavagno Mihai Teodor Lazarescu
• Capacitive sensor and method for sensing changes in a space. national Patent
  Inventors: Luciano Lavagno Mihai Teodor Lazarescu