Ph.D. candidate in Ingegneria Elettrica, Elettronica E Delle Comunicazioni , 39th cycle (2023-2026)
Department of Electronics and Telecommunications (DET)
Adjunct lecturer/Adjunct instructor
Department of Electronics and Telecommunications (DET)
Profile
PhD
Research topic
Acceleration of data center and embedded applications using FPGAs
Tutors
Keywords
Teaching
Teachings
Master of Science
- Modeling and optimization of embedded systems. A.A. 2025/26, INGEGNERIA INFORMATICA (COMPUTER ENGINEERING). Collaboratore del corso
Publications
Latest publications View all publications in Porto@Iris
- Bosio, Roberto; Brignone, Giovanni; Urso, Teodoro; Lazarescu, Mihai T.; Lavagno, ... (2025)
Low-Power Subgraph Isomorphism at the Edge Using FPGAs. In: IEEE ACCESS, vol. 13, pp. 67127-67135. ISSN 2169-3536
Contributo su Rivista - Bosio, Roberto; Minnella, Filippo; Urso, Teodoro; Casu, Mario R.; Lavagno, Luciano; ... (2025)
NN2FPGA: Optimizing CNN Inference on FPGAs With Binary Integer Programming. In: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, vol. 44, pp. 1807-1818. ISSN 0278-0070
Contributo su Rivista - Brignone, Giovanni; Bosio, Roberto; Ottati, Fabrizio; Sansoe', Claudio; Lavagno, Luciano (2025)
SILVIA: Automated Superword-Level Parallelism Exploitation via HLS-Specific LLVM Passes for Compute-Intensive FPGA Accelerators. In: ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS, vol. 18. ISSN 1936-7406
Contributo su Rivista - Bosio, Roberto; Brignone, Giovanni; Minnella, Filippo; Jamal, MUHAMMAD USMAN; Lavagno, ... (2024)
LESS: Low-Power Energy-Efficient Subgraph Isomorphism on FPGA. In: 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), Valencia (Spain), 25-27 March 2024, pp. 1-2. ISBN: 978-3-9819263-8-5
Contributo in Atti di Convegno (Proceeding)