Thu
29
Jan
Seminars and Conferences
Deep test using reverse engineering to address security issues in processors
On Wednesday, 29 January 2026, at 10:00 a.m., a seminar entitled Deep test using reverse engineering to address security issues in processors will be held by professor Ying Zhang.
Abstract
The Chinese government is deeply concerned about the security risks associated with chips and has funded multiple related projects. Hence we are researching the deep test using reverse engineering to address security issues in processors. First, we modelled a class of super-privileged instruction Trojans characterized by an extremely low activation probability and the ability to evade detection by existing methods. Subsequently, we analyzed how such illegal instructions can steal information protected by classical cryptographic algorithms, revealing their capacity to attack Ethereum, steal cryptocurrency, and launder illicit funds. Thereafter, we developed a deep learning-based reverse engineering algorithm to extract chip netlists for deep testing. Finally, we designed an optimized unbounded model check approach to detect anomalous functionality at arbitrary temporal depths. Through this project, we aim to prevent processors with security vulnerabilities from entering critical institutions such as government and military organizations.
Speaker: Ying Zhang - Tonji University (China)
Biography
Ying Zhang, Associate Professor, obtained his PhD from the Institute of Computing Technology, Chinese Academy of Sciences in 2011. He has consistently pursued research in integrated circuit testing, fault tolerance, and security, serving as principal investigator on multiple projects funded by the National Natural Science Foundation of China. He has published over seventy academic papers, including more than ten as first author in IEEE Trans. on CAD, ACM Trans. on DAES, IEEE Trans. on VLSI, and so on. He holds ten nationally authorised invention patents. Additionally, he serves as Guest Editor for the SCI journal INTEGRATION-THE VLSI JOURNAL and as Programme Chair of ITC-Asia. He has also long served as a member of the Technical Committees for many conferences including ASPDAC, ETS, and ATS, and serves as a committee member for the CCF Fault Tolerance Professional Committee, the CCF Integrated Circuit Committee, and the Chinese Society for Metrology and Testing.
The seminar is open to everyone and will take place in person.
For further information, please contact professor Matteo Sonza Reorda.
Abstract
The Chinese government is deeply concerned about the security risks associated with chips and has funded multiple related projects. Hence we are researching the deep test using reverse engineering to address security issues in processors. First, we modelled a class of super-privileged instruction Trojans characterized by an extremely low activation probability and the ability to evade detection by existing methods. Subsequently, we analyzed how such illegal instructions can steal information protected by classical cryptographic algorithms, revealing their capacity to attack Ethereum, steal cryptocurrency, and launder illicit funds. Thereafter, we developed a deep learning-based reverse engineering algorithm to extract chip netlists for deep testing. Finally, we designed an optimized unbounded model check approach to detect anomalous functionality at arbitrary temporal depths. Through this project, we aim to prevent processors with security vulnerabilities from entering critical institutions such as government and military organizations.
Speaker: Ying Zhang - Tonji University (China)
Biography
Ying Zhang, Associate Professor, obtained his PhD from the Institute of Computing Technology, Chinese Academy of Sciences in 2011. He has consistently pursued research in integrated circuit testing, fault tolerance, and security, serving as principal investigator on multiple projects funded by the National Natural Science Foundation of China. He has published over seventy academic papers, including more than ten as first author in IEEE Trans. on CAD, ACM Trans. on DAES, IEEE Trans. on VLSI, and so on. He holds ten nationally authorised invention patents. Additionally, he serves as Guest Editor for the SCI journal INTEGRATION-THE VLSI JOURNAL and as Programme Chair of ITC-Asia. He has also long served as a member of the Technical Committees for many conferences including ASPDAC, ETS, and ATS, and serves as a committee member for the CCF Fault Tolerance Professional Committee, the CCF Integrated Circuit Committee, and the Chinese Society for Metrology and Testing.
The seminar is open to everyone and will take place in person.
For further information, please contact professor Matteo Sonza Reorda.