Ph.D. in Ingegneria Informatica E Dei Sistemi , 28th cycle (2013-2016)
Ph.D. obtained in 2017
Dissertation:
Exploiting Boolean Satisfiability Solvers for High Performance Bit-Level Model Checking
Tutors:
Gianpiero CabodiTeaching
Teachings
Bachelor of Science
- Sistemi operativi. A.A. 2013/14, INGEGNERIA INFORMATICA. Collaboratore del corso
- Sistemi operativi. A.A. 2014/15, INGEGNERIA INFORMATICA. Collaboratore del corso
- Sistemi operativi. A.A. 2015/16, INGEGNERIA INFORMATICA. Collaboratore del corso
- Sistemi operativi. A.A. 2016/17, INGEGNERIA INFORMATICA. Collaboratore del corso
Research
Research groups
Publications
Works published during the Ph.D. View all publications in Porto@Iris
- Cabodi, Gianpiero; Camurati, Paolo Enrico; Palena, Marco; Pasini, Paolo; Vendraminetto, ... (2016)
Reducing Interpolant Circuit Size by Ad Hoc Logic Synthesis and SAT-Based Weakening. In: Formal Methods in Computer-Aided Design, Mountain View, California, USA, October 3 - 6, 2016, pp. 25-32. ISBN: 978-0-9835678-6-8
Contributo in Atti di Convegno (Proceeding) - Cantoro, Riccardo; Palena, Marco; Pasini, Paolo; SONZA REORDA, Matteo (2016)
Test Time Minimization in Reconfigurable Scan Networks. In: 2016 IEEE 25th Asian Test Symposium (ATS), Hiroshima (JP), November 21-24, 2016
Contributo in Atti di Convegno (Proceeding)