Ph.D. in Ingegneria Elettrica, Elettronica E Delle Comunicazioni , 35th cycle (2019-2022)
Ph.D. obtained in 2023
Dissertation:
Improving Quality of Results for High-Level Synthesis based FPGA designs (Abstract)
Tutors:
Luciano Lavagno
Research presentation:
Video presentationProfile
Research topic
Design of prefetching cache unit for FPGA-based accelerators
Research interests
Biography
Publications
Works published during the Ph.D. View all publications in Porto@Iris
- Jamal, MUHAMMAD USMAN; Li, Zhuowei; Lazarescu, MIHAI T.; Lavagno, Luciano (2023)
A Graph Neural Network Model for Fast and Accurate Quality of Result Estimation for High-Level Synthesis. In: IEEE ACCESS, vol. 11, pp. 85785-85798. ISSN 2169-3536
Contributo su Rivista - Jamal, MUHAMMAD USMAN (2023)
Improving Quality of Results for High-Level Synthesis based FPGA designs. relatore: LAVAGNO, Luciano; , 35. XXXV Ciclo, P.: 109
Doctoral Thesis - Brignone, Giovanni; Jamal, Muhammad Usman; Lazarescu, Mihai T.; Lavagno, Luciano (2022)
Array-specific dataflow caches for high-level synthesis of memory-intensive algorithms on FPGAs. In: IEEE ACCESS, vol. 10, pp. 118858-118877. ISSN 2169-3536
Contributo su Rivista