Edgar Ernesto Sanchez Sanchez

ERC sectors

SDG

• Best Paper Award at the IEEE Conference on Design, Automation and Test in Europe conferred by DATE Program Committee, Italy (2006)
• Best Paper award in DDECS 2013 conferred by DDECS organizing committee, Repubblica Ceca (2013)

• 26th IEEE European Test Symposium (24/5/2021-28/5/2021), Program committee
• 25th IEEE European Test Symposium (25/5/2020-1/6/2020), Program committee
• 24th IEEE European Test Symposium (27/5/2019-31/12/2021), Program committee
• 18th IEEE Latin American Test Symposium (1/1/2017-15/3/2017), Program chair

• INGEGNERIA INFORMATICA E DEI SISTEMI, 2024/2025 (40. ciclo)
  Politecnico di TORINO
• INGEGNERIA INFORMATICA E DEI SISTEMI, 2023/2024 (39. ciclo)
  Politecnico di TORINO

• Collegio di Ingegneria Elettronica, delle Telecomunicazioni e Fisica. Componente
• Collegio di Ingegneria Informatica, del Cinema e Meccatronica. Componente

PhD

• Approximate computing paradigms: from component to application-level. A.A. 2020/21, INGEGNERIA INFORMATICA E DEI SISTEMI. Teaching assistant
• Approximate computing paradigms: from component to application-level. A.A. 2019/20, INGEGNERIA INFORMATICA E DEI SISTEMI. Teaching assistant

Master of Science

• HPC (High Performance Computing). A.A. 2025/26, QUANTUM ENGINEERING. Titolare del corso
• Architetture dei sistemi di elaborazione. A.A. 2025/26, INGEGNERIA INFORMATICA (COMPUTER ENGINEERING). Titolare del corso
• HPC (High Performance Computing). A.A. 2024/25, QUANTUM ENGINEERING. Titolare del corso
• Architetture dei sistemi di elaborazione. A.A. 2024/25, INGEGNERIA INFORMATICA (COMPUTER ENGINEERING). Titolare del corso
• HPC (High Performance Computing). A.A. 2023/24, QUANTUM ENGINEERING. Titolare del corso
• Architetture dei sistemi di elaborazione. A.A. 2023/24, INGEGNERIA INFORMATICA (COMPUTER ENGINEERING). Titolare del corso
• Architetture dei sistemi di elaborazione. A.A. 2022/23, INGEGNERIA INFORMATICA (COMPUTER ENGINEERING). Titolare del corso
• Architetture dei sistemi di elaborazione. A.A. 2021/22, INGEGNERIA INFORMATICA (COMPUTER ENGINEERING). Titolare del corso
• Architetture dei sistemi di elaborazione. A.A. 2020/21, INGEGNERIA INFORMATICA (COMPUTER ENGINEERING). Titolare del corso
• Architetture dei sistemi di elaborazione. A.A. 2019/20, INGEGNERIA INFORMATICA (COMPUTER ENGINEERING). Titolare del corso

Bachelor of Science

• Computer sciences. A.A. 2022/23, INGEGNERIA DELL'AUTOVEICOLO (AUTOMOTIVE ENGINEERING). Collaboratore del corso
• Computer sciences. A.A. 2022/23, INGEGNERIA DELL'AUTOVEICOLO (AUTOMOTIVE ENGINEERING). Titolare del corso
• Computer sciences. A.A. 2021/22, INGEGNERIA DELL'AUTOVEICOLO (AUTOMOTIVE ENGINEERING). Collaboratore del corso
• Computer sciences. A.A. 2021/22, INGEGNERIA DELL'AUTOVEICOLO (AUTOMOTIVE ENGINEERING). Titolare del corso
• Computer sciences. A.A. 2020/21, INGEGNERIA DELL'AUTOVEICOLO (AUTOMOTIVE ENGINEERING). Collaboratore del corso
• Computer sciences. A.A. 2020/21, INGEGNERIA DELL'AUTOVEICOLO (AUTOMOTIVE ENGINEERING). Titolare del corso
• Computer sciences. A.A. 2019/20, INGEGNERIA DELL'AUTOVEICOLO (AUTOMOTIVE ENGINEERING). Collaboratore del corso
• Computer sciences. A.A. 2019/20, INGEGNERIA DELL'AUTOVEICOLO (AUTOMOTIVE ENGINEERING). Titolare del corso

Projects funded by competitive calls

• RESCHIP4EU - Reinforcing Skills in Chips Design for Europe, (2024-2028) - Componente gruppo di Ricerca
  University cooperation

• CAD - Electronic CAD & Reliability Group (DAUIN)

Projects funded by competitive calls

• REACT - Self-AwaRe NEuromorphic ArChiTectures: Security, Reliability and Energy-Efficiency, (2025-2029) - Responsabile Scientifico
  UE-funded research - HE - Excellent Science - MSCA

Projects funded by commercial contracts

• Activities for supporting the development of the new Electrical/Electronic Architecture, (2025-2026) - Responsabile Scientifico
  Commercial Research
• New Electrical/Electronic Architecture Pre-study, (2024-2025) - Responsabile Scientifico
  Commercial Research
• Robotics Functional Safety, (2022-2023) - Responsabile contrattuale
  Commercial Research
• Analysis and optimization of Core SelfTest (CST) Libraries running in multi core Automotive Microcontrollers, (2021-2022) - Responsabile Scientifico
  Commercial Research
• Robotics Functional Safety, (2021-2022) - Responsabile Scientifico
  Commercial Research
• Core Self Test (CST) generation able to run in Automotive Microcontrollers multi core devices used for automotive applications, (2020-2020) - Responsabile Scientifico
  Commercial Research
• Core Self Test (CST) generation able to run in Automotive Microcontrollers multi core devices used for automotive applications, (2019-2019) - Responsabile Scientifico
  Commercial Research
• CST generation for a new 40nm Automotive Microcontroller used for automotive applications, (2018-2018) - Responsabile Scientifico
  Commercial Research
• CST generation for a 40nm Automotive Microcontroller, (2017-2017) - Responsabile Scientifico
  Commercial Research

• Behnam Farnaghinejad. Programme in Intelligenza Artificiale (40^th cycle, 2024-in progress)
  Research subject: Improving the security of embedded systems running AI applications
  
  Embedded AI
  TinyML
  Embedded AI
  TinyML
  Embedded AI
  TinyML
• Antonio Porsia. Programme in Ingegneria Informatica E Dei Sistemi (39^th cycle, 2023-in progress)
  
  Computer architectures and Computer aided design
  Computer architectures and Computer aided design
• Juan David Guerrero Balaguera. Programme in Ingegneria Informatica E Dei Sistemi (36^th cycle, 2020-2024)
  Thesis: Reliability Enhancement in GPU Architectures
  
  Cybersecurity
  Life sciences
  Cybersecurity
  Life sciences
• Franco Oberti. Programme in Ingegneria Informatica E Dei Sistemi (36^th cycle, 2020-2024)
  Thesis: Cybersecurity for future interconnected and smart vehicles

• Turco, Vittorio; Fezza, Lorenzo; Ruospo, Annachiara; Sanchez, Ernesto; Sonza Reorda, ... (In stampa)
  APSS Metrics for Fault Detection: Area, Position, Symmetry, and Shape in Image Segmentation. In: DFT 2025 38th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, Barcellona (ESP), 21-23 October 2025
  Contributo in Atti di Convegno (Proceeding)
• Farnaghinejad, Behnam; Bellizia, Davide; Dolmeta, Alessandra; Masera, Guido; Porsia, ... (In stampa)
  Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF). In: International Test Conference 2025, San Diego, California (USA), September 21-26, 2025, pp. 1-10
  Contributo in Atti di Convegno (Proceeding)
• Angione, Francesco; Bernardi, Paolo; Bosio, Alberto; Dattatraya Dixit, Harish; ... (2025)
  Special Session: Trustworthy Hardware-AI at the Cloud. In: IEEE VLSI Test Symposium 2025, Tempe, Arizona (USA), 28-30 April 2025. ISBN: 979-8-3315-2144-8
  Contributo in Atti di Convegno (Proceeding)
• Porsia, Antonio; Perlo, Giacomo; Ruospo, Annachiara; Sanchez, Ernesto (2025)
  On the resilience of INT8 Quantized Neural Networks on Low-Power RISC-V Devices. In: AxC’25 The 10th Workshop on Approximate Computing, Naples (Ita), June 23-26, 2025, pp. 119-122. ISBN: 979-8-3315-1205-7
  Contributo in Atti di Convegno (Proceeding)
• Azziz, Julia; Ruospo, Annachiara; Sanchez, Ernesto; Acle, Julio Pérez (2025)
  Bi-LORD: Bit-Wise Low-Cost Real Numbers Dependability Assessment in AI Applications. In: 26th IEEE Latin American Test Symposium, LATS 2025, San Andres Island (COL), 11-14 March 2025, pp. 1-6. ISBN: 978-1-6654-7764-2
  Contributo in Atti di Convegno (Proceeding)

• A Shannon-Hartley-Based Approach To Measure The Criticality Of Synaptic Weights. international Patent
  Inventors: Annachiara Ruospo Edgar Ernesto Sanchez Sanchez