Behnam Farnaghinejad

Research topic

Improving the security of embedded systems running AI applications

Tutors

• Edgar Ernesto Sanchez Sanchez
• Stefano Di Carlo
• Alessandro Savino

Master of Science

• Architetture dei sistemi di elaborazione. A.A. 2025/26, INGEGNERIA INFORMATICA (COMPUTER ENGINEERING). Collaboratore del corso
• Computer architectures. A.A. 2025/26, INGEGNERIA INFORMATICA (COMPUTER ENGINEERING). Collaboratore del corso

• CAD - Electronic CAD & Reliability Group (DAUIN)

• Farnaghinejad, Behnam; Sanchez, Ernesto (2026)
  Case Study: Integrating RISC-V Zicfiss Shadow Stack Support for Control-Flow Integrity on the CVA6 Processor. In: 27th IEEE Latin American Test Symposium (LATS 2026), Florianópolis (BRA), 17-20 March 2026, pp. 1-2. ISBN: 979-8-3195-4235-9
  Contributo in Atti di Convegno (Proceeding)
• Farnaghinejad, Behnam; Ruospo, Annachiara; Savino, Alessandro; Di Carlo, Stefano; ... (2026)
  Deep Learning-Based Power Side-Channel Evaluation from RTL Switching-Activity Proxies. In: 27th IEEE Latin American Test Symposium (LATS 2026), Florianópolis (BRA), 17-20 March 2026, pp. 1-6. ISBN: 979-8-3195-4235-9
  Contributo in Atti di Convegno (Proceeding)
• Farnaghinejad, Behnam; Bellizia, Davide; Dolmeta, Alessandra; Masera, Guido; Porsia, ... (2025)
  Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF). In: International Test Conference 2025, San Diego, California (USA), September 20-26, 2025, pp. 233-242. ISBN: 979-8-3315-7041-5
  Contributo in Atti di Convegno (Proceeding)
• Farnaghinejad, Behnam; Porsia, Antonio; Ruospo, Annachiara; Savino, Alessandro; Di ... (2025)
  Late Contribution: VeriSide: A Modified Verilator for Leakage Assessment at the RTL Level. In: 26th IEEE Latin American Test Samposium 2025, San Andres Islas (COL), 11-14 March 2025, pp. 1-2. ISBN: 978-1-6654-7763-5
  Contributo in Atti di Convegno (Proceeding)