System-level design of Systems-on-chip (SoC), FPGAs, and ASICs


The research focuses on the development of SoCs with processor cores (e.g., RISC-V) and hardware accelerators specialized for different domains such as machine learning, biomedical imaging, food quality control, and more. The research explores high-level approaches such as synthesis from high-level description and power, performance, and area (PPA) models for improved design-space exploration (DSE). Automatic DSE is another approach that is being studied, which aims to optimize the PPA metrics while reducing the design cycle time. The research investigates different techniques, such as customized hardware blocks, software libraries, and programmable and reconfigurable hardware. Techniques for designing and implementing resilient accelerators are also being investigated to improve system reliability and robustness.

In this line of activity, one goal is to explore and expand the use of high-level synthesis in system-level design, in particular for FPGAs. Application domains include hardware acceleration for data center, machine learning and high-performance computing applications. The objective is both to improve performance and to reduce energy consumption, for both large-scale and embedded applications. The techniques explored include automated implementation of dedicated caches and buffers to speed up DRAM access, as well as global scheduling of multiple accelerators, taking into account resource and memory bandwidth limitations.

ERC sectors 

  • PE6_1 Computer architecture, embedded systems, operating systems
  • PE6_2 Distributed systems, parallel computing, sensor networks, cyber-physical systems
  • PE7_4 (Micro- and nano-) systems engineering


  • System-on-chip
  • Design space exploration
  • High-level synthesis
  • FPGA and ASIC
  • Software acceleration
  • Memory architecture
  • System-level scheduling