Juan David Guerrero Balaguera

Ph.D. candidate in Ingegneria Informatica E Dei Sistemi , 36th cycle (2020-2023)
Department of Control and Computer Engineering (DAUIN)

Research Assistant
Department of Control and Computer Engineering (DAUIN)

Docente esterno e/o collaboratore didattico
Department of Control and Computer Engineering (DAUIN)

Profile

PhD

Thesis title

Reliability Enhancement in GPU Architectures

Research topic

Resilient architectures for AI-oriented applications

Tutors

Research interests

Cybersecurity
Life sciences

Biography

My Name is Juan David Guerrero originally from Colombia. I acquired my Bachelor’s degree in Electronics Engineering at Universidad Pedagogica y Tecnologica de Colombia (UPTC) in 2013 and my master’s degree in Engineering with emphasis on Electronics at the same University in (2017). currently, I'm second year Ph.D student in the Department of Computer and Control Engineering at Politecnico di Torino. In 2013, I won a one-year research assistant position given by the Colombian Government and at same time that position gave me the opportunity to start my Master’s degree studies. In 2015, I won a position as temporary lecturer at UPTC. Since that year, I was in charge of teaching activities about Digital Logic, Computer Architectures, Embedded Systems and Advanced Digital Design for Image Processing. This background allows to me start research collaboration activities with Politecnico di Torino and then it gave me the opportunity to become a PhD student at the same university. During my first year of PhD, I published several papers in different conferences some of them with high prestige, receiving one best paper award in one of these conferences. The following are the conferences in which I have participated so far.
  • Design and Verification of an open-source SFU model for GPGPUs”, 17th Biennial Baltic Electronics Conference (BEC), 2020.
  • On the Functional Test of Special Function Units in GPUs,”24th Int. Symp. Des. Diagnostics Electron. Circuits Syst. DDECS 2021
  • A Novel Compaction Approach for SBST Test Programs, Asian Test Symposium (ATS), Nov-2021.
  • A Compaction Method for STLs for GPU in-field test .DATE 2022
  • Using Hardware Performance Counters to support in-field GPU Testing, 28th IEEE International Conference on Electronics Circuits and Systems, IEEE ICECS 2021
  • Challenges on High-Level STLs Generation for In-field GPU Test, 22nd Workshop on RTL and High-Level Testing, WRTLT 2021.

Awards and Honors

  • PhD Quality Awards 2023 (2023)
  • The DDECS 2021 Program Committee awards Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda for the Best Paper in the Test Field entitled “On the Functional Test of Special Function Units in GPUs" (2021)

Teaching

Teachings

Bachelor of Science

  • Computer sciences. A.A. 2023/24, INGEGNERIA DELL'AUTOVEICOLO (AUTOMOTIVE ENGINEERING). Collaboratore del corso
  • Computer sciences. A.A. 2022/23, INGEGNERIA DELL'AUTOVEICOLO (AUTOMOTIVE ENGINEERING). Collaboratore del corso
  • Computer sciences. A.A. 2021/22, INGEGNERIA DELL'AUTOVEICOLO (AUTOMOTIVE ENGINEERING). Collaboratore del corso
MostraNascondi A.A. passati

Research

Research groups

Publications

PoliTO co-authors

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