Giovanni Brignone

PhD Student in Ingegneria Elettrica, Elettronica E Delle Comunicazioni , 37^th cycle (2021-2024)
Department of Electronics and Telecommunications (DET)

giovanni.brignone@polito.it

Profile

PhD

Research topic

Improving Quality of Results for HLS designs

Tutors

Luciano Lavagno

Research interests

Modeling, simulation and CAD

Biography

Giovanni Brignone received the M.S. degree in Computer Engineering from the Politecnico di Torino (Italy) in 2021, where he is currently pursuing the Ph.D. degree with the Department of Electronics and Telecommunications under the supervision of Prof. L. Lavagno.
His research interests focus on high-level synthesis, digital hardware design, and HW/SW co-design.

Publications

Latest publications View all publications in Porto@Iris

Brignone, Giovanni; Jamal, Muhammad Usman; Lazarescu, Mihai T.; Lavagno, Luciano (2022)
Array-specific dataflow caches for high-level synthesis of memory-intensive algorithms on FPGAs. In: IEEE ACCESS, vol. 10, pp. 118858-118877. ISSN 2169-3536
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