Giovanni Brignone

Dottorando in Ingegneria Elettrica, Elettronica E Delle Comunicazioni , 37^o ciclo (2021-2024)
Dipartimento di Elettronica e Telecomunicazioni (DET)

Docente esterno e/o collaboratore didattico
Dipartimento di Elettronica e Telecomunicazioni (DET)

giovanni.brignone@polito.it

Profilo

Dottorato di ricerca

Titolo della tesi

Making acceleration more amenable with novel high-level synthesis techniques for FPGAs

Argomento di ricerca

Improving Quality of Results for HLS designs

Tutori

Luciano Lavagno

Interessi di ricerca

Modeling, simulation and CAD

Biografia

Giovanni Brignone received the M.S. degree in Computer Engineering from the Politecnico di Torino (Italy) in 2021, where he is currently pursuing the Ph.D. degree with the Department of Electronics and Telecommunications under the supervision of Prof. L. Lavagno.
His research interests focus on high-level synthesis, digital hardware design, and HW/SW co-design.

Didattica

Insegnamenti

Corso di laurea magistrale

Modeling and optimization of embedded systems. A.A. 2024/25, INGEGNERIA INFORMATICA (COMPUTER ENGINEERING). Collaboratore del corso

Pubblicazioni

Pubblicazioni più recenti Vedi tutte le pubblicazioni su Porto@Iris

Brignone, Giovanni; Bosio, Roberto; Ottati, Fabrizio; Sansoe', Claudio; Lavagno, Luciano (In stampa)
SILVIA: Automated Superword-Level Parallelism Exploitation via HLS-Specific LLVM Passes for Compute-Intensive FPGA Accelerators. In: ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS. ISSN 1936-7406
Contributo su Rivista
Bosio, Roberto; Brignone, Giovanni; Minnella, Filippo; Jamal, MUHAMMAD USMAN; Lavagno, ... (2024)
LESS: Low-Power Energy-Efficient Subgraph Isomorphism on FPGA. In: 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), Valencia (Spain), 25-27 March 2024, pp. 1-2. ISBN: 978-3-9819263-8-5
Contributo in Atti di Convegno (Proceeding)
Ottati, Fabrizio; Gao, Chang; Chen, Qinyu; Brignone, Giovanni; Casu, Mario Roberto; ... (2023)
To Spike or Not To Spike: A Digital Hardware Perspective on Deep Learning Acceleration. In: IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, vol. 13, pp. 1015-1025. ISSN 2156-3365
Contributo su Rivista
Brignone, Giovanni; Lazarescu, Mihai T.; Lavagno, Luciano (2023)
A DSP shared is a DSP earned: HLS Task-Level Multi-Pumping for High-Performance Low-Resource Designs. In: 2023 IEEE 41st International Conference on Computer Design (ICCD), Washington (USA), 06-08 November 2023, pp. 551-557. ISBN: 979-8-3503-4291-8
Contributo in Atti di Convegno (Proceeding)
Brignone, Giovanni; Jamal, Muhammad Usman; Lazarescu, Mihai T.; Lavagno, Luciano (2022)
Array-specific dataflow caches for high-level synthesis of memory-intensive algorithms on FPGAs. In: IEEE ACCESS, vol. 10, pp. 118858-118877. ISSN 2169-3536
Contributo su Rivista