Research database


37 months (2009 - 2012)
Principal investigator(s):
Project type:
UE-funded research - VII PQ - COOPERATION - ICT
Project identification number:


The main objective of the COMPLEX project is to increase the competitiveness of the European semiconductor, system integrator and EDA industry by addressing the problem of platform-based design space exploration under consideration of power and performance constraints early in the design process. High performance usually causes high power consumption. A main challenge in today's embedded system design is to find the perfect balance between performance and power. This balance can not be found efficiently and at high quality, because until now no generic framework for accurately and jointly estimating performance and power consumption starting at the algorithmic level is available. This can only be achieved in cooperation on a European level, taking into account European platform providers, system developers/integrators, EDA companies, Universities and research institutes from both, the HW and the embedded SW world.
The COMPLEX project will enable the European semiconductor and electronic system industry to achieve a break through in product quality through substantially improved performance and power efficiency. This quantum leap will be achieved by a new design environment for platform-based design-space exploration offering developers of next-generation mobile and embedded systems a highly efficient and productive design methodology and tool chain allowing them to iteratively explore and refine their applications to meet market requirements. The design technology in particular enables the fast simulation and assessment of the platform at Electronic System Level (ESL) with up to cycle accuracy at the earliest instant in the design process. Several new modelling, exploration and simulation concepts will be developed and combined with well established ESL synthesis, cross-compilation, analysis and simulation tools into a seamless holistic design flow enabling performance & power aware virtual prototyping from a combined hardware-software perspective.

People involved