Michele Caon

Borsista
Dipartimento di Elettronica e Telecomunicazioni (DET)

Docente esterno e/o collaboratore didattico
Dipartimento di Elettronica e Telecomunicazioni (DET)

Dottorando in Ingegneria Elettrica, Elettronica E Delle Comunicazioni , 36^o cycle (2020-2023)
Dipartimento di Elettronica e Telecomunicazioni (DET)

michele.caon@polito.it

Profilo

Dottorato di ricerca

Argomento di ricerca

Design of a modular execution pipeline for LEN5, an out-of-order RISC-V processor

Tutori

Research presentation

Poster

Interessi di ricerca

VLSI theory, design and applications

Biografia

Michele Caon received his BSc and MSc (with honours) in Electronics Engineering at Politecnico di Torino in 2017 and 2019 respectively. In his Master's thesis he designed a modular execution pipeline for an out-of-order 64-bit RISC-V processor, using Tomasulo's approach to dynamic scheduling. In 2020, he collaborated as a Research Assistant at Politenico di Torino to the Horizon 2020 project EO-ALERT, mainly focusing on the design and development of the software supporting the compression and encryption of Earth observation images. In late 2020 he joined the VLSI Lab, where he is currently pursuing the PhD in Electrical, Electronics and Communications Engineering under the supervision of Prof. Maurizio Martina. His current research topics focus around the design of innovative programmable computing systems, includign out-of-order architectures for RISC-V microprocessors and energy-efficient near-memory vector porcessing units.

Didattica

Insegnamenti

Corso di laurea magistrale

Workshop "SoC Verification Strategies". A.A. 2021/22, INGEGNERIA ELETTRONICA (ELECTRONIC ENGINEERING). Collaboratore del corso
Workshop "SoC Verification Strategies". A.A. 2022/23, INGEGNERIA ELETTRONICA (ELECTRONIC ENGINEERING). Collaboratore del corso

MostraNascondi A.A. passati

Corso di laurea di 1° livello

Digital systems electronics. A.A. 2021/22, INGEGNERIA ELETTRONICA. Collaboratore del corso