Ph.D. candidate in Ingegneria Elettrica, Elettronica E Delle Comunicazioni , 39th cycle (2023-2026)
Department of Electronics and Telecommunications (DET)
Profile
PhD
Research topic
Acceleration of data center and embedded applications using FPGAs
Tutors
Research interests
Biography
In 2020, I earned my Bachelor's degree in Computer Science from Politecnico di Torino. Eager to deepen my understanding of technology, I pursued a Master's degree in Electronics Engineering with a specialized focus on Embedded Systems applications. My thesis focused on enhancing a subgraph isomorphism solver by adapting the algorithm to follow the dataflow paradigm, capitalizing on the unique advantages FPGAs offer compared to other architectures. My current research revolves around crafting accelerators tailored for FPGAs, using the High-Level Synthesis approach. I am actively engaged in optimizing convolutional neural networks, spanning from model quantization to execution on embedded FPGAs.
Publications
Latest publications View all publications in Porto@Iris
- Bosio, Roberto; Minnella, Filippo; Urso, Teodoro; Casu, Mario R.; Lavagno, Luciano; ... (2024)
NN2FPGA: Optimizing CNN Inference on FPGAs With Binary Integer Programming. In: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. ISSN 0278-0070
Contributo su Rivista - Brignone, Giovanni; Bosio, Roberto; Ottati, Fabrizio; Sansoe', Claudio; Lavagno, Luciano (2024)
SILVIA: Automated Superword-Level Parallelism Exploitation via HLS-Specific LLVM Passes for Compute-Intensive FPGA Accelerators. In: ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS. ISSN 1936-7406
Contributo su Rivista - Bosio, Roberto; Brignone, Giovanni; Minnella, Filippo; Jamal, MUHAMMAD USMAN; Lavagno, ... (2024)
LESS: Low-Power Energy-Efficient Subgraph Isomorphism on FPGA. In: 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), Valencia (Spain), 25-27 March 2024, pp. 1-2. ISBN: 978-3-9819263-8-5
Contributo in Atti di Convegno (Proceeding)