Lorenzo Lagostina

Ph.D. candidate in Ingegneria Elettrica, Elettronica E Delle Comunicazioni , 39^th cycle (2023-2026)
Department of Electronics and Telecommunications (DET)

Docente esterno e/o collaboratore didattico
Department of Electronics and Telecommunications (DET)

lorenzo.lagostina@polito.it

Profile

PhD

Research topic

EDA, Embedded Machine Learning

Tutors

Research interests

Big Data, Machine Learning, Neural Networks and Data Science

Modeling, simulation and CAD

VLSI theory, design and applications

Biography

Lorenzo Lagostina received the electronics and communications engineering from the Politecnico di Torino, Torino, Italy, in 2022. He is currently a Ph.D. student in the Department of Electronics and Telecommunications of the Politecnico di Torino. His research interests include Electronic Design Automation (EDA), and Embedded Machine Learning. In 2022 he received the second prize in the IEEE R8 Student Paper Contest at the MELECON22 conference.

Teaching

Teachings

Master of Science

Microelettronica digitale. A.A. 2023/24, INGEGNERIA ELETTRONICA (ELECTRONIC ENGINEERING). Collaboratore del corso

Publications

Latest publications View all publications in Porto@Iris

Lagostina, Lorenzo; Minnella, Filippo; Cortadella, Jordi; Casu, Mario R.; Lazarescu, ... (2024)
Mix & Latch: Comparison With State-of-the-Art Retiming On a RISC-V Benchmark. In: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. ISSN 0278-0070
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