Anagrafe della ricerca

Currently, huge and complex HPC (High-Performance Computing) systems represent strategic systems for supporting various processes and applications, including scientific computing and financial domains. However, the required reliability for their operation necessitates efficient and intelligent mechanisms for identifying any possible hardware fault, particularly during field operation. The probability of occurrence of such faults increases not only with the complexity of HPC systems but also due to the technological evolution of electronic devices. This technology vulnerability highlights the need for a new generation of fault detection mechanisms in hardware to avoid or handle data and workload corruption [1,2]. The complexity and heterogeneity of HPC systems increasingly complicate the detection and identification of any hardware faults within them. Such faults may produce failures that can interfere with Artificial Intelligence applications that frequently participate in critical flows and/or processes. It is therefore essential to have tools and methods for the timely detection and identification of any faults in the system. Therefore, the main objective of the project is to develop efficient techniques for identifying hardware faults in HPC systems during the operational phase, with particular attention to architectures used for executing Artificial Intelligence applications (processors, memories, hardware accelerators). The planned activities also aim to assess the cost and ease of integration into existing flows of the proposed techniques, including the use of appropriate test cases that can be provided by the ISP.

• INTESA SANPAOLO S.P.A. - Coordinatore
• POLITECNICO DI TORINO - AMMINISTRAZIONE CENTRALE