Specification and simulation of digital systems. A.A. 2025/26, INGEGNERIA INFORMATICA (COMPUTER ENGINEERING). Collaboratore del corso
Specification and simulation of digital systems. A.A. 2024/25, INGEGNERIA INFORMATICA (COMPUTER ENGINEERING). Collaboratore del corso
Specification and simulation of digital systems. A.A. 2023/24, INGEGNERIA INFORMATICA (COMPUTER ENGINEERING). Collaboratore del corso

Research

Publications

Urgese, Gianvito; Fra, Vittorio; Pignata, Andrea; Fanuli, Giuseppe; Gomez, Walter ... (2026)
The inNuCE Research Infrastructure and the Neuromorphic MLOps for AIoT prototyping. In: IEEE INTERNET OF THINGS JOURNAL, vol. 13, pp. 19286-19299. ISSN 2327-4662
Contributo su Rivista
Barocci, Michelangelo; Fra, Vittorio; Macii, Enrico; Urgese, Gianvito (2026)
Heterogeneous SoC integrating an open-source recurrent SNN accelerator for neuromorphic edge computing on FPGA. In: ECML PKDD 2024 - "Deep Learning meets Neuromorphic Hardware" workshop, Vilnius (Lituania), 09/09/2024 - 14/09/2024, pp. 128-143. ISSN 1865-0929. ISBN: 978-3-032-25311-8
Contributo in Atti di Convegno (Proceeding)
Barocci, Michelangelo (2023)
Hybrid digital-neuromorphic architecture integration for low-power applications. In: Forum on specification & Design Languages, Torino, September 13-15, 2023
Contributo in Atti di Convegno (Proceeding)
Barocci, Michelangelo; Fra, Vittorio; Macii, Enrico; Urgese, Gianvito (2023)
Review of open neuromorphic architectures and a first integration in the RISC-V PULP platform. In: 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-2023), Singapore, December 18-21, 2023, pp. 470-477. ISBN: 979-8-3503-9361-3
Contributo in Atti di Convegno (Proceeding)