PhD Student in Ingegneria Elettrica, Elettronica E Delle Comunicazioni , 36th cycle (2020-2023)
Department of Electronics and Telecommunications (DET)
Docente esterno e/o collaboratore didattico
Department of Electronics and Telecommunications (DET)
Profile
PhD
Research topic
Eco-Algorithms. Energy saving in data centers
Tutors
Research interests
Biography
After that I decided to enroll for the Master degree in Electronics Engineering choosing a curriculum that focuses mainly in Embedded Systems applications.
Thanks to second level courses, I had the chance to experience different digital architectures, to acquire knowledge related to digital design and synthesis, and to collaborate with different students in order to develop specific projects.
I developed the Master thesis in the framework of the Inner Tracking System update at CERN, the goal was to obtain a radiation hardened soft-core for specific FPGA devices. After that, I graduated in April 2018.
Here is a link to the thesis pdf file: https://webthesis.biblio.polito.it/7536/1/tesi.pdf.
From February 2018 to October 2020 I worked as digital designer for STMicroelectronics Powertrain and Safety division; here I was able to deepen my knowledge regarding ASIC design and verification, experiencing different automotive applications and learning industrial standards for devices development and safety requirements.
Starting from November 2020 I am working as PhD student for Politecnico di Torino doctoral program in Electrical, Electronics and Communications Engineering.
The object of this PhD is to explore state of the art solutions in terms of energy saving for data centers and to find new algorithms and architectures able to reach this goal.
Teaching
Teachings
Master of Science
- Modeling and optimization of embedded systems. A.A. 2022/23, INGEGNERIA INFORMATICA (COMPUTER ENGINEERING). Collaboratore del corso
Publications
Latest publications View all publications in Porto@Iris
- Minnella, Filippo; CORTADELLA FORTUNY, Jordi; Casu, Mario R.; Lazarescu, Mihai T.; ... (2023)
Mix & Latch: An Optimization Flow for High-Performance Designs with Single-Clock Mixed-Polarity Latches and Flip-Flops. In: IEEE ACCESS, pp. 1-1. ISSN 2169-3536
Contributo su Rivista
Society and Enterprise
Patents and other intellectual properties
- MIx&Latch: a method to increase the operating frequency of synchronous digital circuits using a single clock tree and a mixed distribution of sequential elements. national Patent
Inventors: Mario Roberto Casu Luciano Lavagno Filippo Minnella